A VLSI Architecture for Variable Block Size Video Motion Estimation
Data(s) |
01/07/2004
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Resumo |
With the advent of new video standards such as MPEG-4 part-10 and H.264/H.26L, demands for advanced video coding, particularly in the area of variable block size video motion estimation (VBSME), are increasing. In this paper, we propose a new one-dimensional (1-D) very large-scale integration architecture for full-search VBSME (FSVBSME). The VBS sum of absolute differences (SAD) computation is performed by re-using the results of smaller sub-block computations. These are distributed and combined by incorporating a shuffling mechanism within each processing element. Whereas a conventional 1-D architecture can process only one motion vector (MV), this new architecture can process up to 41 MV sub-blocks (within a macroblock) in the same number of clock cycles. |
Formato |
application/pdf |
Identificador |
http://dx.doi.org/10.1109/TCSII.2004.829555 http://pure.qub.ac.uk/ws/files/382633/IEEEtransME.pdf http://www.scopus.com/inward/record.url?scp=3543021496&partnerID=8YFLogxK |
Idioma(s) |
eng |
Direitos |
info:eu-repo/semantics/restrictedAccess |
Fonte |
Yap , S Y & McCanny , J 2004 , ' A VLSI Architecture for Variable Block Size Video Motion Estimation ' IEEE Transactions on Circuits and Systems II: Express Briefs , vol 51(7) , no. 7 , pp. 384-389 . DOI: 10.1109/TCSII.2004.829555 |
Palavras-Chave | #/dk/atira/pure/subjectarea/asjc/1700/1711 #Signal Processing #/dk/atira/pure/subjectarea/asjc/2200/2208 #Electrical and Electronic Engineering |
Tipo |
article |