Germanium MOS Capacitors with Hafnium Dioxide and Silicon Dioxide Dielectrics

Germanium (Ge) does not grow a suitable oxide for MOS devices. The Ge/dielectric interface is of prime importance to the operation of photo-detectors and scaled MOSTs. Therefore there is a requirement for deposited or bonded dielectric materials. MOS capacitors have been formed on germanium substrates with three different dielectric materials. Firstly, a thermally grown and bonded silicon dioxide (SiO2) layer, secondly, SiO2 deposited by atmospheric pressure CVD ‘silox’, and thirdly a hafnium oxide (HfO2) high-k dielectric deposited by atomic layer deposition (ALD). Ge wafers used were p-type 1 0 0 2 O cm. C–V measurements have been made on all three types of capacitors to assess the interface quality. ALD HfO2 and silox both display acceptable C–V characteristics. Threshold voltage and maximum and minimum capacitance values closely match expected values found through calculation. However, the bonded SiO2 has non-ideal C–V characteristics, revealing the presence of a high density of interface states. A H2/N2 post metal anneal has a detrimental effect on C–V characteristics of HfO2 and silox dielectrics, causing a shift in the threshold voltage and rise in the minimum capacitance value. In the case of hafnium dioxide, capacitor properties can be improved by performing a plasma nitridation of the Ge surface prior to dielectric deposition.

Generic Architecture and Semiconductor Intellectual Property Cores for Avanced Encryption Standard Cryptography

A generic architecture for implementing the advanced encryption standard (AES) encryption algorithm in silicon is proposed. This allows the instantiation of a wide range of chip specifications, with these taking the form of semiconductor intellectual property (IP) cores. Cores implemented from this architecture can perform both encryption and decryption and support four modes of operation: (i) electronic codebook mode; (ii) output feedback mode; (iii) cipher block chaining mode; and (iv) ciphertext feedback mode. Chip designs can also be generated to cover all three AES key lengths, namely 128 bits, 192 bits and 256 bits. On-the-fly generation of the round keys required during decryption is also possible. The general, flexible and multi-functional nature of the approach described contrasts with previous designs which, to date, have been focused on specific implementations. The presented ideas are demonstrated by implementation in FPGA technology. However, the architecture and IP cores derived from this are easily migratable to other silicon technologies including ASIC and PLD and are capable of covering a wide range of modem communication systems cryptographic requirements. Moreover, the designs produced have a gate count and throughput comparable with or better than the previous one-off solutions.

Fabrication of Sub-micron Active Layer SSOI Substrates using Ion Splitting and Wafer Bonding Technologies

This paper reports the fabrication of SSOI (Silicon on Silicide On Insulator) substrates with active silicon regions only 0.5mum thick, incorporating LPCVD low resistivity tungsten silicide (WSix) as the buried layer. The substrates were produced using ion splitting and two stages of wafer bonding. Scanning acoustic microscope imaging confirmed that the bond interfaces are essentially void-free. These SSOI wafers are designed to be employed as substrates for mm-wave reflect-array diodes, and the required selective etch technology is described together with details of a suitable device.

Surface plasmons in layered structures with semiconductor and metallic films

The complete spectrum of eigenwaves including surface plasmon polaritons (SPP), dynamic (bulk) and complex waves in the layered structures containing semiconductor and metallic films has been explored. The effects of loss, geometry and the parameters of dielectric layers on the eigenmode spectrum and, particularly, on the SPP modes have been analysed using both the asymptotic and rigorous numerical solutions of the full-wave dispersion equation. The field and Poynting vector distributions have been examined to identify the modes and elucidate their properties. It has been shown that losses and dispersion of permittivity qualitatively alter the spectral content and the eigenwave properties. The SPP counter-directional power fluxes in the film and surrounding dielectrics have been attributed to vortices of power flow, which are responsible for the distinctive features of SPP modes. It has been demonstrated for the first time that the maximal attainable slow-wave factor of the SPP modes guided by thin Au films at optical frequencies is capped not by losses but the frequency dispersion of the actual Au permittivity. © 2009 EDP Sciences.