Tungsten Silicide Contacts to Polycrystalline Silicon and Silicon-Germanium Alloys

Novel CVD WSi2 technology with low series and contact resistance in SiGe HBTs was achieved. Specific contact resistance to Si1-xGex with 0

Germanium MOS Capacitors with Hafnium Dioxide and Silicon Dioxide Dielectrics

Germanium (Ge) does not grow a suitable oxide for MOS devices. The Ge/dielectric interface is of prime importance to the operation of photo-detectors and scaled MOSTs. Therefore there is a requirement for deposited or bonded dielectric materials. MOS capacitors have been formed on germanium substrates with three different dielectric materials. Firstly, a thermally grown and bonded silicon dioxide (SiO2) layer, secondly, SiO2 deposited by atmospheric pressure CVD ‘silox’, and thirdly a hafnium oxide (HfO2) high-k dielectric deposited by atomic layer deposition (ALD). Ge wafers used were p-type 1 0 0 2 O cm. C–V measurements have been made on all three types of capacitors to assess the interface quality. ALD HfO2 and silox both display acceptable C–V characteristics. Threshold voltage and maximum and minimum capacitance values closely match expected values found through calculation. However, the bonded SiO2 has non-ideal C–V characteristics, revealing the presence of a high density of interface states. A H2/N2 post metal anneal has a detrimental effect on C–V characteristics of HfO2 and silox dielectrics, causing a shift in the threshold voltage and rise in the minimum capacitance value. In the case of hafnium dioxide, capacitor properties can be improved by performing a plasma nitridation of the Ge surface prior to dielectric deposition.

Atomic layer deposition of hafnium oxide dielectrics on silicon and germanium substrates

Hafnium oxide films have been deposited at 250 °C on silicon and germanium substrates by atomic layer deposition (ALD), using tetrakis-ethylmethylamino hafnium (TEMAH) and water vapour as precursors in a modified Oxford Instruments PECVD system. Self-limiting monolayer growth has been verified, characterised by a growth rate of 0.082 nm/ cycle. Layer uniformity is approximately within ±1% of the mean value. MOS capacitors have been fabricated by evaporating aluminium electrodes. CV analysis has been used to determine the bulk and interface properties of the HfO 2, and their dependence on pre-clean schedule, deposition conditions and post-deposition annealing. The dielectric constant of the HfO 2 is typically 18. On silicon, best results are obtained when the HfO 2 is deposited on a chemically oxidised hydrophilic surface. On germanium, best results are obtained when the substrate is nitrided before HfO 2 deposition, using an in-situ nitrogen plasma treatment. © Springer Science+Business Media, LLC 2007.

Germanium on Sapphire By Wafer Bonding

This paper describes the creation of a germanium on sapphire platform, via wafer bonding technology, for system-on-a-chip applications. Similar thermal coefficients of expansion between germanium (5.8 x 10-6 K-1) and sapphire (5 x 10-6 K-1) make the bonding of germanium to sapphire a reality. Germanium directly bonded to sapphire results in microvoid generation during post bond annealing. Inclusion of an interface layer such as silicon dioxide layer by plasma enhanced chemical vapour deposition, prior to bonding, results in a microvoid free bond interface after annealing. Grinding and polishing of the subsequent germanium layer has been achieved leaving a thick germanium on sapphire (GeOS) substrate. Submicron GeOS layers have also been achieved with hydrogen/helium co-implantation and layer transfer. Circular geometry transistors exhibiting a field effect mobility of 890 cm2/V s have been fabricated onto the thick germanium on sapphire layer.

Germanium bonding to AI2O3

Germanium has been bonded to both single crystal Al2O 3 (sapphire) as well as fine grain Al2O3. A germanium to sapphire bonding energy of 3 J/m2 has been measured after a 200 °C bond anneal. Micro voids formed between the germanium/sapphire interface can be removed by employing an interfacial layer of silicon dioxide on either surface. Patterning the sapphire into a grid pattern prior to bonding creates an escape path for trapped gas or moisture allowing micro void free direct bonding to be achieved. Modifying the surface of the fine grain Al2O3 surface with a polycrystalline silicon deposition and polish creates a surface, having an rms roughness (measured over a 250© m2 area), of 1.5nm, suitable for bonding. Techniques employed in the germanium sapphire bonding can then be used in the bonding of fine grain A12O3 to germanium. © The Electrochemical Society.

(Invited) Germanium on Sapphire Technology

Silicon-on-sapphire (SOS) substrates have been proven to offer significant advantages in the integration of passive and active devices in RF circuits. Germanium on insulator technology is a candidate for future higher performance circuits. Thus the advantages of employing a low loss dielectric substrate other than a silicon-dioxide layer on silicon will be even greater. This paper covers the production of germanium on sapphire (GeOS) substrates by wafer bonding. The quality of the germanium back interface is studied and a tungsten self-aligned gate process MOST process has been developed. High low field mobilities of 450-500 cm2/V-s have been achieved for p-channel MOSTs produced on GeOS substrates. Thick germanium on alumina (GOAL) substrates have also been produced.

Optimisation and scaling of interfacial GeO2 layers for high-k gate stacks on germanium and extraction of dielectric constant of GeO2

Germanium is an attractive channel material for MOSFETs because of its higher mobility than silicon. In this paper, GeO2 has been investigated as an interfacial layer for high-kappa gate stacks on germanium. Thermally grown GeO2 layers have been prepared at 550 degrees C to minimise GeO volatilisation. GeO2 growth has been performed in both pure O-2 ambient and O-2 diluted with N-2. GeO2 thickness has been scaled down to approximately 3 nm. MOS capacitors have been fabricated using different GeO2 thicknesses with a standard high-kappa dielectric on top. Electrical properties and thermal stability have been tested up to at least 350 degrees C. The K value of GeO2 was experimentally determined to be 4.5. Interface state densities (D-it) of less than 10(12) CM-2 eV(-1) have been extracted for all devices using the conductance method.

Brittle-ductile transition during diamond turning of single crystal silicon carbide

In this experimental study, diamond turning of single crystal 6H-SiC was performed at a cutting speed of 1 m/s on an ultra-precision diamond turning machine (Moore Nanotech 350 UPL) to elucidate the microscopic origin of ductile-regime machining. Distilled water (pH value 7) was used as a preferred coolant during the course of machining in order to improve the tribological performance. A high magnification scanning electron microscope (SEM FIB- FEI Quanta 3D FEG) was used to examine the cutting tool before and after the machining. A surface finish of Ra=9.2 nm, better than any previously reported value on SiC was obtained. Also, tremendously high cutting resistance was offered by SiC resulting in the observation of significant wear marks on the cutting tool just after 1 km of cutting length. It was found out through a DXR Raman microscope that similar to other classical brittle materials (silicon, germanium, etc.) an occurrence of brittle-ductile transition is responsible for the ductile-regime machining of 6H-SiC. It has also been demonstrated that the structural phase transformations associated with the diamond turning of brittle materials which are normally considered as a prerequisite to ductile-regime machining, may not be observed during ductile-regime machining of polycrystalline materials.

Diamond machining of silicon: A review of advances in molecular dynamics simulation

Molecular dynamics (MD) simulation has enhanced our understanding about ductile-regime machining of brittle materials such as silicon and germanium. In particular, MD simulation has helped understand the occurrence of brittle–ductile transition due to the high-pressure phase transformation (HPPT), which induces Herzfeld–Mott transition. In this paper, relevant MD simulation studies in conjunction with experimental studies are reviewed with a focus on (i) the importance of machining variables: undeformed chip thickness, feed rate, depth of cut, geometry of the cutting tool in influencing the state of the deviatoric stresses to cause HPPT in silicon, (ii) the influence of material properties: role of fracture toughness and hardness, crystal structure and anisotropy of the material, and (iii) phenomenological understanding of the wear of diamond cutting tools, which are all non-trivial for cost-effective manufacturing of silicon. The ongoing developmental work on potential energy functions is reviewed to identify opportunities for overcoming the current limitations of MD simulations. Potential research areas relating to how MD simulation might help improve existing manufacturing technologies are identified which may be of particular interest to early stage researchers.