6-T SRAM cell design with nanoscale double-gate SOI MOSFETs: impact of source/drain engineering and circuit topology

The impact of source/drain engineering on the performance of a six-transistor (6-T) static random access memory (SRAM) cell, based on 22 nm double-gate (DG) SOI MOSFETs, has been analyzed using mixed-mode simulation, for three different circuit topologies for low voltage operation. The trade-offs associated with the various conflicting requirements relating to read/write/standby operations have been evaluated comprehensively in terms of eight performance metrics, namely retention noise margin, static noise margin, static voltage/current noise margin, write-ability current, write trip voltage/current and leakage current. Optimal design parameters with gate-underlap architecture have been identified to enhance the overall SRAM performance, and the influence of parasitic source/drain resistance and supply voltage scaling has been investigated. A gate-underlap device designed with a spacer-to-straggle (s/sigma) ratio in the range 2-3 yields improved SRAM performance metrics, regardless of circuit topology. An optimal two word-line double-gate SOI 6-T SRAM cell design exhibits a high SNM similar to 162 mV, I-wr similar to 35 mu A and low I-leak similar to 70 pA at V-DD = 0.6 V, while maintaining SNM similar to 30% V-DD over the supply voltage (V-DD) range of 0.4-0.9 V.

External circuit system effects on chlorine plasma instabilities

The effects of the external circuit on plasma instabilities in all inductive plasma source are investigated. The instabilities are found to be asymmetric with respect to the circuit input impedance. A simplified model of the antenna-plasnia coupling provides an explanation of the asymetry.

Control of leaky-mode propagation and radiation properties in hybrid dielectric-waveguide printed-circuit technology: Experimental results

Experimental results are presented to show how a planar circuit, printed on a laterally shielded dielectric waveguide, can induce and control the radiation from a leaky-mode. By studying the leaky-mode complex propagation constant, a desired radiation pattern can be synthesized, controlling the main radiation characteristics (pointing direction, beamwidth, sidelobes level) for a given frequency, This technique leads to very flexible and original leaky-wave antenna designs. The experiments show to be in very good agreement with the leaky-mode theory.

Current transients in the small salient-pole alternator caused by sudden short-circuit and synchronisation events

Small salient-pole machines, in the range 30 kVA to 2 MVA, are often used in distributed generators, which in turn are likely to form the major constituent of power generation in power system islanding schemes or microgrids. In addition to power system faults, such as short-circuits, islanding contains an inherent risk of out-of-synchronism re-closure onto the main power system. To understand more fully the effect of these phenomena on a small salient-pole alternator, the armature and field currents from tests conducted on a 31.5 kVA machine are analysed. This study demonstrates that by resolving the voltage difference between the machine terminals and bus into direct and quadrature axis components, interesting properties of the transient currents are revealed. The presence of saliency and short time-constants cause intriguing differences between machine events such as out-of-phase synchronisations and sudden three-phase short-circuits.

Design and implementation of a field programmable CRC circuit architecture

The design and implementation of a programmable cyclic redundancy check (CRC) computation circuit architecture, suitable for deployment in network related system-on-chips (SoCs) is presented. The architecture has been designed to be field reprogrammable so that it is fully flexible in terms of the polynomial deployed and the input port width. The circuit includes an embedded configuration controller that has a low reconfiguration time and hardware cost. The circuit has been synthesised and mapped to 130-nm UMC standard cell [application-specific integrated circuit (ASIC)] technology and is capable of supporting line speeds of 5 Gb/s. © 2006 IEEE.

A scalable packet sorting circuit for high-speed WFQ packet scheduling

A novel implementation of a tag sorting circuit for a weighted fair queueing (WFQ) enabled Internet Protocol (IP) packet scheduler is presented. The design consists of a search tree, matching circuitry, and a custom memory layout. It is implemented using 130-nm silicon technology and supports quality of service (QoS) on networks at line speeds of 40 Gb/s, enabling next generation IP services to be deployed.