A scalable packet sorting circuit for high-speed WFQ packet scheduling
| Data(s) |
01/07/2008
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| Resumo |
A novel implementation of a tag sorting circuit for a weighted fair queueing (WFQ) enabled Internet Protocol (IP) packet scheduler is presented. The design consists of a search tree, matching circuitry, and a custom memory layout. It is implemented using 130-nm silicon technology and supports quality of service (QoS) on networks at line speeds of 40 Gb/s, enabling next generation IP services to be deployed. |
| Identificador | |
| Idioma(s) |
eng |
| Direitos |
info:eu-repo/semantics/closedAccess |
| Fonte |
McLaughlin , K , Sezer , S , Blume , H , Yang , X , Kupzog , F & Noll , T 2008 , ' A scalable packet sorting circuit for high-speed WFQ packet scheduling ' IEEE Transactions on Very Large Scale Integration (VLSI) Systems , vol 16 , no. 7 , 4553746 , pp. 781-791 . DOI: 10.1109/TVLSI.2008.2000323 |
| Palavras-Chave | #Packet scheduling #traffic management #quality of servcie #QoS #lookup #sorting #fair queuing #WFQ #time-stamp #/dk/atira/pure/subjectarea/asjc/2200/2208 #Electrical and Electronic Engineering #/dk/atira/pure/subjectarea/asjc/1700/1708 #Hardware and Architecture |
| Tipo |
article |
