Thin film sputtered silicon for silicon wafer bonding applications

The transfer of functional integrated circuit layers to other substrates is being investigated for smart-sensors, MEMS, 3-D ICs and mixed semiconductor circuits. There is a need for a planarisation and bondable layer which can be deposited at low temperature and which is IC compatible. This paper describes for the first time the successful use of sputtered silicon in this role for applications as outlined above where high temperature post bond anneals are not required. It also highlights the problems of using sputtered silicon as a bonding layer in applications where post bond temperatures greater than 400C are required.

Toward Self-Assembled Ferroelectric Random Access Memories: Hard-Wired Switching Capacitor Arrays with Almost Tb/in.2 Densities

We report on the successful fabrication of arrays of switchable nanocapacitors made by harnessing the self-assembly of materials. The structures are composed of arrays of 20-40 nm diameter Pt nanowires, spaced 50-100 nm apart, electrodeposited through nanoporous alumina onto a thin film lower electrode on a silicon wafer. A thin film ferroelectric (both barium titanate (BTO) and lead zirconium titanate (PZT)) has been deposited on top of the nanowire array, followed by the deposition of thin film upper electrodes. The PZT nanocapacitors exhibit hysteresis loops with substantial remnant polarizations, while although the switching performance was inferior, the low-field characteristics of the BTO nanocapacitors show dielectric behavior comparable to conventional thin film heterostructures. While registration is not sufficient for commercial RAM production, this is nevertheless an embryonic form of the highest density hard-wired FRAM capacitor array reported to date and compares favorably with atomic force microscopy read-write densities.

Perturbed frequency-selective surfaces fabricated on large thin polymer membranes for multiband infrared applications

The design, fabrication, and characterization of single-screen perturbed frequency-selective surfaces (FSS) at infrared frequencies for single and multiband applications are reported. Single-band FSS based on parallel strips have been perturbed by decreasing the length of every second strip within the array in order to achieve dual band-stop responses. The same principle has been extended to design FSS exhibiting tri- and quadreflection bands. In addition, strip FSSs have been perturbed by replacing every second strip for a metallic ring, resulting in dual-band filters with different polarization responses of the bands. These designs have been fabricated on large thin polyimide membranes using sacrificial silicon wafers. An oxide interlayer between the sacrificial silicon wafer and the polyimide membrane is employed to stop the silicon etching and is wet etched subsequently by a solution of ammonium fluoride and acetic acid that does not attack either the polyimide membrane or the aluminium FSS elements. Fourier transform infrared spectroscopy measurements are presented to validate the predicted responses of the fabricated prototypes.

An investigation of Mode I fracture toughness using aligned carbon nanotube forests at the crack interface

This paper presents a novel approach for introducing aligned carbon nanotubes (CNTs) at the crack interface of pre-impregnated (prepreg) carbon fibre composite plies, creating a hierarchical (three-phase) composite structure. The aim of this approach is to improve the interlaminar fracture toughness. The developed method for transplanting the aligned CNTs from the silicon wafer onto the pre-preg material is described. Scanning electron microscopy (SEM) was used to analyse the effects of the transplantation method. Double Cantilever Beam (DCB) specimens were prepared, according to ASTM standard D5528- 01R07E03 [1] and aligned multi-walled carbon nanotubes (MWCNTs) were introduced at the crack-tip. Mode I fracture tests for pristine (control) specimens and CNT-enhanced specimens were conducted and an average increase in the critical strain energy release rate (GIc) of approximately 50 % was achieved.

Laser annealing of sputtered silicon for wafer-bonding applications

Sputtered silicon is investigated as a bonding layer for transfer of pre-processed silicon layers to various insulating substrates. Although the material appears suitable for low temperature processing, previous work has shown that gas trapped in the pores of the sputtered material is released at temperatures above 350 degrees C and further increases of temperature lead to destruction of any bonded interface. Pre-annealing at 1000 degrees C before bonding drives out gas and/or seals the surface, but for device applications where processing temperatures must be kept below about 300 degrees C, this technique cannot be used. In the current work, we have investigated the effect of excimer laser-annealing to heat the sputtered silicon surface to high temperature whilst minimising heating of the underlying substrate. Temperature profile simulations are presented and the results of RBS, TEM and AFM used to characterise the annealed layers. The results verify that gases are present in the sub-surface layers and suggest that while sealing of the surface is important for suppression of the out-diffusion of gases, immediate surface gas removal may also play a role. The laser-annealing technique appears to be an effective method of treating sputtered silicon, yielding a low roughness surface suitable for wafer bonding, thermal splitting and layer transfer.

Fabrication of Sub-micron Active Layer SSOI Substrates using Ion Splitting and Wafer Bonding Technologies

This paper reports the fabrication of SSOI (Silicon on Silicide On Insulator) substrates with active silicon regions only 0.5mum thick, incorporating LPCVD low resistivity tungsten silicide (WSix) as the buried layer. The substrates were produced using ion splitting and two stages of wafer bonding. Scanning acoustic microscope imaging confirmed that the bond interfaces are essentially void-free. These SSOI wafers are designed to be employed as substrates for mm-wave reflect-array diodes, and the required selective etch technology is described together with details of a suitable device.

Germanium on Sapphire By Wafer Bonding

This paper describes the creation of a germanium on sapphire platform, via wafer bonding technology, for system-on-a-chip applications. Similar thermal coefficients of expansion between germanium (5.8 x 10-6 K-1) and sapphire (5 x 10-6 K-1) make the bonding of germanium to sapphire a reality. Germanium directly bonded to sapphire results in microvoid generation during post bond annealing. Inclusion of an interface layer such as silicon dioxide layer by plasma enhanced chemical vapour deposition, prior to bonding, results in a microvoid free bond interface after annealing. Grinding and polishing of the subsequent germanium layer has been achieved leaving a thick germanium on sapphire (GeOS) substrate. Submicron GeOS layers have also been achieved with hydrogen/helium co-implantation and layer transfer. Circular geometry transistors exhibiting a field effect mobility of 890 cm2/V s have been fabricated onto the thick germanium on sapphire layer.