How (In)Consistent is the Court of Justice in the Application of the Market Access Test?”

Invited panel speaker at a Jean Monnet Chair funded research workshop organised by the Europa Institute, School of Law, University of Edinburgh (9 December 2011), http://www.pol.ed.ac.uk/research_themes/index/jean_monnet_centre_of_excellence/principles_of_market_access_workshop

Addressing the technical and market challenges to high wind power integration in Ireland

Over the last decade there has been a rapid global increase in wind power stimulated by energy and climate policies. However, as wind power is inherently variable and stochastic over a range of time scales, additional system balancing is required to ensure system reliability and stability. This paper reviews the technical, policy and market challenges to achieving ambitious wind power penetration targets in Ireland’s All-Island Grid and examines a number of measures proposed to address these challenges. Current government policy in Ireland is to address these challenges with additional grid reinforcement, interconnection and open-cycle gas plant. More recently smart grid combined with demand side management and electric vehicles have also been presented as options to mitigate the variability of wind power. In addition, the transmission system operators have developed wind farm specific grid codes requiring improved turbine controls and wind power forecasting techniques.

Market Basket Survey Shows Elevated Levels of As in South Central U.S. Processed Rice Compared to California: Consequences for Human Dietary Exposure:consequences for human dietary exposure

We report the largest market basket survey of arsenic (As) in U.S. rice to date. Our findings show differences in transitional-metal levels between polished and unpolished rice and geographical variation in As and selenium (Se) between rice processed in California and the South Central U.S. The mean and median As grain levels for the South Central U.S. were 0.30 and 0.27 µg As g-1, respectively, for 107 samples. Levels for California were 41% lower than the South Central U.S., with a mean of 0.17 µg As g-1 and a median of 0.16 µg As g-1 for 27 samples. The mean and median Se grain levels for the South Central U.S. were 0.19 µg Se g-1. Californian rice levels were lower, averaging only 0.08 and 0.06 µg Se g-1 for mean and median values, respectively. The difference between the two regions was found to be significant for As and Se (General Linear Model (GLM):? As p < 0.001; Se p < 0.001). No statistically significant differences were observed in As or Se levels between polished and unpolished rice (GLM:? As p = 0.213; Se p = 0.113). No significant differences in grain levels of manganese (Mn), cobalt (Co), copper (Cu), or zinc (Zn) were observed between California and the South Central U.S. Modeling arsenic intake for the U.S. population based on this survey shows that for certain groups (namely Hispanics, Asians, sufferers of Celiac disease, and infants) dietary exposure to inorganic As from elevated levels in rice potentially exceeds the maximum intake of As from drinking water (based on consumption of 1 L of 0.01 mg L-1 In. As) and Californian state exposure limits. Further studies on the transformation of As in soil, grain As bioavailability in the human gastrointestinal tract, and grain elemental speciation trends are critical.

High performance VLSI architecture for division and square root

A novel high performance bit parallel architecture to perform square root and division is proposed. Relevant VLSI design issues have been addressed. By employing redundant arithmetic and a semisystolic schedule, the throughput has been made independent of the size of the array.

A VLSI architecture for multiplication, division and square root

A high-performance VLSI architecture to perform combined multiply-accumulate, divide, and square root operations is proposed. The circuit is highly regular, requires only minimal control, and can be reconfigured for every cycle. The execution time for each operation is the same. The combination of redundancy and pipelining results in a throughput independent of the wordsize of the array. With current CMOS technology, throughput rates in excess of 80 million operations per second are achievable.

VLSI module for high-performance multiply, square root and divide

A high-performance VLSI architecture to perform multiply-accumulate, division and square root operations is proposed. The circuit is highly regular, requires only minimal control and can be pipelined right down to the bit level. The system can also be reconfigured on every cycle to perform any one of these operations. The gate count per row has been estimated at (27n+70) gate equivalents where n is the divisor wordlength. The throughput rate, which equals the clock speed, is the same for each operation and is independent of the wordlength. This is achieved through the combination of pipelining and redundant arithmetic. With a 1.0 µm CMOS technology and extensive pipelining, throughput rates in excess of 70 million operations per second are expected.

Fast VLSI algorithms for division and square root

Real time digital signal processing demands high performance implementations of division and square root. This can only be achieved by the design of fast and efficient arithmetic algorithms which address practical VLSI architectural design issues. In this paper, new algorithms for division and square root are described. The new schemes are based on pre-scaling the operands and modifying the classical SRT method such that the result digits and the remainders are computed concurrently and the computations in adjacent rows are overlapped. Consequently, their performance exceeds that of the SRT methods. The hardware cost for higher radices is considerably more than that of the SRT methods but for many applications, this is not prohibitive. A system of equations is presented which enables both an analysis of the method for any radix and the parameters of implementations to be easily determined. This is illustrated for the case of radix 2 and radix 4. In addition, a highly regular array architecture combining the division and square root method is described. © 1994 Kluwer Academic Publishers.