139 resultados para nanotube arrays


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High harmonic generation (HHG) is a central driver of the rapidly growing field of ultrafast science. We present a novel quasiphase-matching (QPM) concept with a dual-gas multijet target leading, for the first time, to remarkable phase control between multiple HHG sources (> 2) within the Rayleigh range. The alternating jet structure with driving and matching zones shows perfect coherent buildup for up to six QPM periods. Although not in the focus of the proof-of-principle studies presented here, we achieved competitive conversion efficiencies already in this early stage of development.

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Introduction Juvenile idiopathic arthritis (JIA) is a heterogeneous disease characterized by chronic joint inflammation of unknown cause in children. JIA is an autoimmune disease and small numbers of auto-antibodies have been reported in JIA patients. The identification of antibody markers could improve the existing clinical management of patients. Methods A pilot study was performed on the application of a high-throughput platform, nucleic acid programmable protein arrays (NAPPA), to assess the levels of antibodies present in the systemic circulation and synovial joint of a small cohort of juvenile arthritis patients. Plasma and synovial fluid from ten JIA patients was screened for antibodies against 768 proteins on NAPPA. Results Quantitative reproducibility of NAPPA was demonstrated with >0.95 intra- and inter- array correlations. A strong correlation was also observed for the levels of antibodies between plasma and synovial fluid across the study cohort (r=0.96). Differences in the levels of 18 antibodies were revealed between sample types across all patients. Patients were segregated into two clinical subtypes with distinct antibody signatures by unsupervised hierarchical cluster analysis. Conclusions NAPPA provides a high-throughput quantitatively reproducible platform to screen for disease specific autoantibodies at the proteome level on a microscope slide. The strong correlation between the circulating antibody levels and those of the inflamed joint represents a novel finding and provides confidence to use plasma for discovery of autoantibodies in JIA, thus circumventing the challenges associated with joint aspiration. We expect that autoantibody profiling of JIA patients on NAPPA could yield antibody markers that can act as criteria to stratify patients, predict outcomes and understand disease etiology at the molecular level.

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Domain patterns consisting of triangular nanodomains of less than 50 nm size, arranged into long regular vertex arrays separated by stripe domains, were observed by (scanning and high-resolution) transmission electron microscopy and piezoresponse force microscopy in BiFeO3 single crystals grown from solution flux. Piezoresponse force microscopy analysis together with crystallographic analysis by selected area and nanobeam electron diffraction indicate that these patterns consist of ferroelectric 109 degrees domains. A possibility for conserving Kittel's law is discussed in terms of the patterns being confined to the skin layer observed recently on BiFeO3 single crystals.

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Unique microneedle arrays prepared from crosslinked polymers, which contain no drug themselves, are described. They rapidly take up skin interstitial fluid upon skin insertion to form continuous, unblockable, hydrogel conduits from attached patch-type drug reservoirs to the dermal microcirculation. Importantly, such microneedles, which can be fabricated in a wide range of patch sizes and microneedle geometries, can be easily sterilized, resist hole closure while in place, and are removed completely intact from the skin. Delivery of macromolecules is no longer limited to what can be loaded into the microneedles themselves and transdermal drug delivery is now controlled by the crosslink density of the hydrogel system rather than the stratum corneum, while electrically modulated delivery is also a unique feature. This technology has the potential to overcome the limitations of conventional microneedle designs and greatly increase the range of the type of drug that is deliverable transdermally, with ensuing benefits for industry, healthcare providers and, ultimately, patients.

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We investigate the collective optomechanics of an ensemble of scatterers inside a Fabry-Pérot resonator and identify an optimized configuration where the ensemble is transmissive, in contrast to the usual reflective optomechanics approach. In this configuration, the optomechanical coupling of a specific collective mechanical mode can be several orders of magnitude larger than the single-element case, and long-range interactions can be generated between the different elements since light permeates throughout the array. This new regime should realistically allow for achieving strong single-photon optomechanical coupling with massive resonators, realizing hybrid quantum interfaces, and exploiting collective long-range interactions in arrays of atoms or mechanical oscillators.

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The initial part of this paper reviews the early challenges (c 1980) in achieving real-time silicon implementations of DSP computations. In particular, it discusses research on application specific architectures, including bit level systolic circuits that led to important advances in achieving the DSP performance levels then required. These were many orders of magnitude greater than those achievable using programmable (including early DSP) processors, and were demonstrated through the design of commercial digital correlator and digital filter chips. As is discussed, an important challenge was the application of these concepts to recursive computations as occur, for example, in Infinite Impulse Response (IIR) filters. An important breakthrough was to show how fine grained pipelining can be used if arithmetic is performed most significant bit (msb) first. This can be achieved using redundant number systems, including carry-save arithmetic. This research and its practical benefits were again demonstrated through a number of novel IIR filter chip designs which at the time, exhibited performance much greater than previous solutions. The architectural insights gained coupled with the regular nature of many DSP and video processing computations also provided the foundation for new methods for the rapid design and synthesis of complex DSP System-on-Chip (SoC), Intellectual Property (IP) cores. This included the creation of a wide portfolio of commercial SoC video compression cores (MPEG2, MPEG4, H.264) for very high performance applications ranging from cell phones to High Definition TV (HDTV). The work provided the foundation for systematic methodologies, tools and design flows including high-level design optimizations based on "algorithmic engineering" and also led to the creation of the Abhainn tool environment for the design of complex heterogeneous DSP platforms comprising processors and multiple FPGAs. The paper concludes with a discussion of the problems faced by designers in developing complex DSP systems using current SoC technology. © 2007 Springer Science+Business Media, LLC.

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The use of systolic arrays of 1-bit cells to implement a range of important signal processing functions is demonstrated. Two examples, a pipelined multiplier and a pipelined bit-slice transform circuit, are given. This approach has many important implications for silicon technology, and these are outlined.

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Bit level systolic array structures for computing sums of products are studied in detail. It is shown that these can be sub-divided into two classes and that, within each class, architectures can be described in terms of a set of constraint equations. It is further demonstrated that high performance system level functions with attractive VLSI properties can be constructed by matching data flow geometries in bit level and word level architectures.

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Bit-level systolic-array structures for computing sums of products are studied in detail. It is shown that these can be subdivided into two classes and that within each class architectures can be described in terms of a set of constraint equations. It is further demonstrated that high-performance system-level functions with attractive VLSI properties can be constructed by matching data-flow geometries in bit-level and word-level architectures.

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A systolic array is an array of individual processing cells each of which has some local memory and is connected only to its nearest neighbours in the form of a regular lattice. On each cycle of a simple clock every cell receives data from its neighbouring cells and performs a specific processing operation on it. The resulting data is stored within the cell and passed on to neighbouring cells on the next clock cycle. This paper gives an overview of work to date and illustrates the application of bit-level systolic arrays by means of two examples: (1) a pipelined bit-slice circuit for computing matrix x vector transforms; and (2) a bit serial structure for multi-bit convolution.

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The mapping of matrix multiplied by matrix multiplication onto both word and bit level systolic arrays has been investigated. It has been found that well defined word and bit level data flow constraints must be satisfied within such circuits. An efficient and highly regular bit level array has been generated by exploiting the basic compatibilities in data flow symmetries at each level of the problem. A description of the circuit which emerges is given and some details relating to its practical implementation are discussed.

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The use of bit-level systolic array circuits as building blocks in the construction of larger word-level systolic systems is investigated. It is shown that the overall structure and detailed timing of such systems may be derived quite simply using the dependence graph and cut-set procedure developed by S. Y. Kung (1988). This provides an attractive and intuitive approach to the bit-level design of many VLSI signal processing components. The technique can be applied to ripple-through and partly pipelined circuits as well as fully systolic designs. It therefore provides a means of examining the relative tradeoff between levels of pipelining, chip area, power consumption, and throughput rate within a given VLSI design.

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A bit-level systolic array system for performing a binary tree vector quantization (VQ) codebook search is described. This is based on a highly regular VLSI building block circuit. The system in question exhibits a very high data rate suitable for a range of real-time applications. A technique is described which reduces the storage requirements of such a system by 50%, with a corresponding decrease in hardware complexity.