Atomic excitation during recollision-free ultrafast multi-electron tunnel ionization

Modern intense ultrafast pulsed lasers generate an electric field of sufficient strength to permit tunnel ionization of the valence electrons in atoms(1). This process is usually treated as a rapid succession of isolated events, in which the states of the remaining electrons are neglected(2). Such electronic interactions are predicted to be weak, the exception being recollision excitation and ionization caused by linearly polarized radiation(3). In contrast, it has recently been suggested that intense field ionization may be accompanied by a two-stage 'shake-up' reaction(4). Here we report a unique combination of experimental techniques(5-8) that allows us to accurately measure the tunnel ionization probability for argon exposed to 50-fs laser pulses. Most significantly for the current study, this measurement is independent of the optical focal geometry(7,8), equivalent to a homogenous electric field. Furthermore, circularly polarized radiation negates recollision. The present measurements indicate that tunnel ionization results in simultaneous excitation of one or more remaining electrons through shake-up(9). From an atomic physics standpoint, it may be possible to induce ionization from specific states, and will influence the development of coherent attosecond extreme-ultraviolet-radiation sources(10). Such pulses have vital scientific and economic potential in areas such as high-resolution imaging of in vivo cells and nanoscale extreme-ultraviolet lithography.

Field configured assembly: Programmed manipulation and self-assembly at the mesoscale

Field configured assembly is a programmable force field method that permits rapid, "hands-free" manipulation, assembly, and integration of mesoscale objects and devices. In this method, electric fields, configured by specific addressing of receptor and counter electrode sites pre-patterned at a silicon chip substrate, drive the field assisted transport, positioning, and localization of mesoscale devices at selected receptor locations. Using this approach, we demonstrate field configured deterministic and stochastic self-assembly of model mesoscale devices, i.e., 50 mum diameter, 670 nm emitting GaAs-based light emitting diodes, at targeted receptor sites on a silicon chip. The versatility of the field configured assembly method suggests that it is applicable to self-assembly of a wide variety of functionally integrated nanoscale and mesoscale systems.

C-60 as a Faraday cage

Endohedral fullerenes have been proposed for a number of technological uses, for example, as a nanoscale switch, memory bit and as qubits for quantum computation. For these technology applications, it is important to know the ease with which the endohedral atom can be manipulated using an applied electric field. We find that the Buckminsterfullerene (C-60) acts effectively as a small Faraday cage, with only 25% of the field penetrating the interior of the molecule. Thus influencing the atom is difficult, but as a qubit the endohedral atom should be well shielded from environmental electrical noise. We also predict how the field penetration should increase with the fullerene radius. (C) 2004 American Institute of Physics.

Broken symmetry and pseudogaps in ropes of carbon nanotubes

Since the discovery of carbon nanotubes, it has been speculated that these materials should behave like nanoscale wires with unusual electronic properties and exceptional strength. Recently, 'ropes' of close-packed single-wall nanotubes have been synthesized in high yield. The tubes in these ropes are mainly of the (10,10) type3, which is predicted to be metallic. Experiments on individual nanotubes and ropes indicate that these systems indeed have transport properties that qualify them to be viewed as nanoscale quantum wires at low temperature. It has been expected that the close-packing of individual nanotubes into ropes does not change their electronic properties significantly. Here, however, we present first-principles calculations which show that a broken symmetry of the (10,10) tube caused by interactions between tubes in a rope induces a pseudogap of about 0.1 eV at the Fermi level. This pseudogap strongly modifies many of the fundamental electronic properties: we predict a semimetal-like temperature dependence of the electrical conductivity and a finite gap in the infrared absorption spectrum. The existence of both electron and hole charge carriers will lead to qualitatively different thermopower and Hall-effect behaviours from those expected for a normal metal.

Electron-phonon interaction in atomic-scale conductors: Einstein oscillators versus full phonon modes

Two extreme pictures of electron-phonon interactions in nanoscale conductors are compared: one in which the vibrations are treated as independent Einstein atomic oscillators, and one in which electrons are allowed to couple to the full, extended phonon modes of the conductor. It is shown that, under a broad range of conditions, the full-mode picture and the Einstein picture produce essentially the same net power at any given atom in the nanojunction. The two pictures begin to differ significantly in the limit of low lattice temperature and low applied voltages, where electron-phonon scattering is controlled by the detailed phonon energy spectrum. As an illustration of the behaviour in this limit, we study the competition between trapped vibrational modes and extended modes in shaping the inelastic current-voltage characteristics of one-dimensional atomic wires.

Tight-binding simulation of current-carrying nanostructures

The tight-binding (TB) approach to the modelling of electrical conduction in small structures is introduced. Different equivalent forms of the TB expression for the electrical current in a nanoscale junction are derived. The use of the formalism to calculate the current density and local potential is illustrated by model examples. A first-principles time-dependent TB formalism for calculating current-induced forces and the dynamical response of atoms is presented. An earlier expression for current-induced forces under steady-state conditions is generalized beyond local charge neutrality and beyond orthogonal TB. Future directions in the modelling of power dissipation and local heating in nanoscale conductors are discussed.

Current-induced forces in atomic-scale conductors

We present a self-consistent tight-binding formalism to calculate the forces on individual atoms due to the flow of electrical current in atomic-scale conductors. Simultaneously with the forces, the method yields the local current density and the local potential in the presence of current flow, allowing a direct comparison between these quantities. The method is applicable to structures of arbitrary atomic geometry and can be used to model current-induced mechanical effects in realistic nanoscale junctions and wires. The formalism is implemented within a simple Is tight-binding model and is applied to two model structures; atomic chains and a nanoscale wire containing a vacancy.

Creation of damage-free ferroelectric nanocapacitors via focused ion beam milling

We present a novel method for creating damage-free ferroelectric nanostructures with a focused ion beam milling machine. Using a standard e-beam photoresist followed by a dilute acid wash, nanostructures ranging in size from 1 mu m down to 250 nm were created in a 90 nm thick lead zirconate titanate ( PZT) wafer. Transmission electron microscopy and piezoresponse force microscopy ( PFM) confirmed that the surfaces of the nanostructures remained damage free during fabrication, and showed no gallium implantation, and that there was no degradation of ferroelectric properties. In fact DC strain loops, obtained using PFM, demonstrated that the nanostructures have a higher piezoresponse than unmilled films. As the samples did not have any top hard mask, the method presented is unique as it allows for imaging of the top surface to understand edge effects in well-defined nanostructures. In addition, as no post-mill annealing was necessary, it facilitates investigation of nanoscale domain mechanisms without process-induced artefacts.

Ancients inspire modern memory

A stencilling technique for depositing arrays of nanoscale ferroelectric capacitors on a surface could be useful in data storage devices.

Liquid source misted chemical deposition process of three-dimensional nano-ferroelectrics with substrate heating

A modification of liquid source misted chemical deposition process (LSMCD) with heating mist and substrate has developed, and this enabled to control mist penetrability and fluidity on sidewalls of three-dimensional structures and ensure step coverage. A modified LSMCD process allowed a combinatorial approach of Pb(Zr,Ti)O-3 (PZT) thin films and carbon nanotubes (CNTs) toward ultrahigh integration density of ferroelectric random access memories (FeRAMs). The CNTs templates were survived during the crystallization process of deposited PZT film onto CNTs annealed at 650 degrees C in oxygen ambient due to a matter of minute process, so that the thermal budget is quite small. The modified LSMCD process opens up the possibility to realize the nanoscale capacitor structure of ferroelectric PZT film with CNTs electrodes toward ultrahigh integration density FeRAMs.

Improving f(MAX)/f(T) ratio in FinFETs using source/drain extension region engineering

A design methodology to optimise the ratio of maximum oscillation frequency to cutoff frequency, f(MAX)/f(T), in 60 nm FinFETs is presented. Results show that 25 to 60% improvement in f(MAX)/f(T) at drain currents of 20-300 mu A/mu m can be achieved in a non-overlap gate-source/drain architecture. The reported work provides new insights into the design and optimisation of nanoscale FinFETs for RF applications.

High tolerance to gate misalignment in low voltage gate-underlap double gate MOSFETs

.In this letter, we demonstrate for the first time that gate misalignment is not a critical limiting factor for low voltage operation in gate-underlap double gate (DG) devices. Our results show that underlap architecture significantly extends the tolerable limit of gate misalignment in 25 nm devices. DG MOSFETs with high degree of gate misalignment and optimal gate-underlap design can perform comparably or even better than self-aligned nonunderlap devices. Results show that spacer-to-straggle (s/sigma) ratio, a key design parameter for underlap devices, should be within the range of 2.3-3.0 to accommodate back gate misalignment. These results are very significant as the stringent process control requirements for achieving self-alignment in nanoscale planar DG MOSFETs are considerably relaxed

Performance projections and design optimization of planar double gate SOI MOSFETs for logic technology applications

In this paper, by investigating the influence of source/drain extension region engineering (also known as gate-source/drain underlap) in nanoscale planar double gate (DG) SOI MOSFETs, we offer new insights into the design of future nanoscale gate-underlap DG devices to achieve ITRS projections for high performance (HP), low standby power (LSTP) and low operating power (LOP) logic technologies. The impact of high-kappa gate dielectric, silicon film thickness, together with parameters associated with the lateral source/drain doping profile, is investigated in detail. The results show that spacer width along with lateral straggle can not only effectively control short-channel effects, thus presenting low off-current in a gate underlap device, but can also be optimized to achieve lower intrinsic delay and higher on-off current ratio (I-on/I-off). Based on the investigation of on-current (I-on), off-current (I-off), I-on/I-off, intrinsic delay (tau), energy delay product and static power dissipation, we present design guidelines to select key device parameters to achieve ITRS projections. Using nominal gate lengths for different technologies, as recommended from ITRS specification, optimally designed gate-underlap DG MOSFETs with a spacer-to-straggle (s/sigma) ratio of 2.3 for HP/LOP and 3.2 for LSTP logic technologies will meet ITRS projection. However, a relatively narrow range of lateral straggle lying between 7 to 8 nm is recommended. A sensitivity analysis of intrinsic delay, on-current and off-current to important parameters allows a comparative analysis of the various design options and shows that gate workfunction appears to be the most crucial parameter in the design of DG devices for all three technologies. The impact of back gate misalignment on I-on, I-off and tau is also investigated for optimized underlap devices.

Design and optimization of FinFETs for ultra-low-voltage analog applications

In this paper, we analyze the enormous potential of engineering source/drain extension (SDE) regions in FinFETs for ultra-low-voltage (ULV) analog applications. SDE region design can simultaneously improve two key analog figures of merit (FOM)-intrinsic de gain (A(vo)) and cutoff frequency (f(T)) for 60 and 30 nm FinFETs operated at low drive current (J(ds) = 5 mu A/mu m). The improved Avo and fT are nearly twice compared to those of devices with abrupt SDE regions. The influence of the SDE region profile and its impact on analog FOM is extensively analyzed. Results show that SDE region optimization provides an additional degree of freedom apart from device parameters (fin width and aspect ratio) to design future nanoscale analog devices. The results are analyzed in terms of spacer-to-straggle ratio a new design parameter for SDE engineered devices. This paper provides new opportunities for realizing future ULV/low-power analog design with FinFETs.

Source/drain extension region engineering in FinFETs for low-voltage analog applications

In this letter, we propose a novel design methodology for engineering source/drain extension (SDE) regions to simultaneously improve intrinsic dc gain (A(vo)) and cutoff frequency (f(T)) of 25-nm gate-length FinFETs operated at low drain-current (I-ds = 10 mu A/mu m). SDE region optimization in 25-nm FinFETs results in exceptionally high values of Avo (similar to 45 dB) and f(T) (similar to 70 GHz), which is nearly 2.5 times greater when compared to devices designed with abrupt SDE regions. The influence of spacer width, lateral source/drain doping gradient, and the spacer-to-gradient ratio on key analog figures of merit is examined in detail. This letter provides new opportunities for realizing future low-voltage/low-power analog design with nanoscale SDE-engineered FinFETs.