Evaluating Asymmetric Multicore Systems-on-Chip using Iso-Metrics

The end of Dennard scaling has pushed power consumption into a first order concern for current systems, on par with performance. As a result, near-threshold voltage computing (NTVC) has been proposed as a potential means to tackle the limited cooling capacity of CMOS technology. Hardware operating in NTV consumes significantly less power, at the cost of lower frequency, and thus reduced performance, as well as increased error rates. In this paper, we investigate if a low-power systems-on-chip, consisting of ARM's asymmetric big.LITTLE technology, can be an alternative to conventional high performance multicore processors in terms of power/energy in an unreliable scenario. For our study, we use the Conjugate Gradient solver, an algorithm representative of the computations performed by a large range of scientific and engineering codes.

A high performance IIR digital filter chip

The design of a high-performance IIR (infinite impulse response) digital filter is described. The chip architecture operates on 11-b parallel, two's complement input data with a 12-b parallel two's complement coefficient to produce a 14-b two's complement output. The chip is implemented in 1.5-µm, double-layer-metal CMOS technology, consumes 0.5 W, and can operate up to 15 Msample/s. The main component of the system is a fine-grained systolic array that internally is based on a signed binary number representation (SBNR). Issues addressed include testing, clock distribution, and circuitry for conversion between two's complement and SBNR.

Investigation of chip formation and fracture toughness in orthogonal cutting of UD-CFRP

Features of chip formation can inform the mechanism of a machining process. In this paper, a series of orthogonal cutting experiments were carried out on unidirectional carbon fiber reinforced polymer (UD-CFRP) under cutting speed of 0.5 m/min. The specially designed orthogonal cutting tools and high-speed camera were used in this paper. Two main factors are found to influence the chip morphology, namely the depth of cut (DOC) and the fiber orientation (angle 휃), and the latter of which plays a more dominant role. Based on the investigation of chip formation, a new approach is proposed for predicting fracture toughness of the newly machined surface and the total energy consumption during CFRP orthogonal cutting is introduced as a function of the surface energy of machined surface, the energy consumed to overcome friction, and the energy for chip fracture. The results show that the proportion of energy spent on tool-chip friction is the greatest, and the proportions of energy spent on creating new surface decrease with the increasing of fiber angle.

High Strength Thermoplastic Bonding for Multi-channel, Multi-layer Lab-on-Chip Devices for Ocean and Environmental applications

A solvent-vapour thermoplastic bonding process is reported which provides high strength bonding of PMMA over a large area for multi-channel and multi-layer microfluidic devices with shallow high resolution channel features. The bond process utilises a low temperature vacuum thermal fusion step with prior exposure of the substrate to chloroform (CHCl3) vapour to reduce bond temperature to below the PMMA glass transition temperature. Peak tensile and shear bond strengths greater than 3 MPa were achieved for a typical channel depth reduction of 25 µm. The device-equivalent bond performance was evaluated for multiple layers and high resolution channel features using double-side and single-side exposure of the bonding pieces. A single-sided exposure process was achieved which is suited to multi-layer bonding with channel alignment at the expense of greater depth loss and a reduction in peak bond strength. However, leak and burst tests demonstrate bond integrity up to at least 10 bar channel pressure over the full substrate area of 100 mm x 100 mm. The inclusion of metal tracks within the bond resulted in no loss of performance. The vertical wall integrity between channels was found to be compromised by solvent permeation for wall thicknesses of 100 µm which has implications for high resolution serpentine structures. Bond strength is reduced considerably for multi-layer patterned substrates where features on each layer are not aligned, despite the presence of an intermediate blank substrate. Overall a high performance bond process has been developed that has the potential to meet the stringent specifications for lab-on-chip deployment in harsh environmental conditions for applications such as deep ocean profiling.

Evaluating fault tolerance on asymmetric multicore systems-on-chip using iso-metrics

The end of Dennard scaling has promoted low power consumption into a firstorder concern for computing systems. However, conventional power conservation schemes such as voltage and frequency scaling are reaching their limits when used in performance-constrained environments. New technologies are required to break the power wall while sustaining performance on future processors. Low-power embedded processors and near-threshold voltage computing (NTVC) have been proposed as viable solutions to tackle the power wall in future computing systems. Unfortunately, these technologies may also compromise per-core performance and, in the case of NTVC, xreliability. These limitations would make them unsuitable for HPC systems and datacenters. In order to demonstrate that emerging low-power processing technologies can effectively replace conventional technologies, this study relies on ARM’s big.LITTLE processors as both an actual and emulation platform, and state-of-the-art implementations of the CG solver. For NTVC in particular, the paper describes how efficient algorithm-based fault tolerance schemes preserve the power and energy benefits of very low voltage operation.

Mapping protein-DNA interactions using ChIP-sequencing

Chromatin immunoprecipitation (ChIP) allows enrichment of genomic regions which are associated with specific transcription factors, histone modifications, and indeed any other epitopes which are present on chromatin. The original ChIP methods used site-specific PCR and Southern blotting to confirm which regions of the genome were enriched, on a candidate basis. The combination of ChIP with genomic tiling arrays (ChIP-chip) allowed a more unbiased approach to map ChIP-enriched sites. However, limitations of microarray probe design and probe number have a detrimental impact on the coverage, resolution, sensitivity, and cost of whole-genome tiling microarray sets for higher eukaryotes with large genomes. The combination of ChIP with high-throughput sequencing technology has allowed more comprehensive surveys of genome occupancy, greater resolution, and lower cost for whole genome coverage. Herein, we provide a comparison of high-throughput sequencing platforms and a survey of ChIP-seq analysis tools, discuss experimental design, and describe a detailed ChIP-seq method.Chromatin immunoprecipitation (ChIP) allows enrichment of genomic regions which are associated with specific transcription factors, histone modifications, and indeed any other epitopes which are present on chromatin. The original ChIP methods used site-specific PCR and Southern blotting to confirm which regions of the genome were enriched, on a candidate basis. The combination of ChIP with genomic tiling arrays (ChIP-chip) allowed a more unbiased approach to map ChIP-enriched sites. However, limitations of microarray probe design and probe number have a detrimental impact on the coverage, resolution, sensitivity, and cost of whole-genome tiling microarray sets for higher eukaryotes with large genomes. The combination of ChIP with high-throughput sequencing technology has allowed more comprehensive surveys of genome occupancy, greater resolution, and lower cost for whole genome coverage. Herein, we provide a comparison of high-throughput sequencing platforms and a survey of ChIP-seq analysis tools, discuss experimental design, and describe a detailed ChIP-seq method.

Chromatin immunoprecipitation (ChIP) methodology and readouts

The identification of direct nuclear hormone receptor gene targets provides clues to their contribution to both development and cancer progression. Until recently, the identification of such direct target genes has relied on a combination of expression analysis and in silico searches for consensus binding motifs in gene promoters. Consensus binding motifs for transcription factors are often defined using in vitro DNA binding strategies. Such in vitro strategies fail to account for the many factors that contribute significantly to target selection by transcription factors in cells beyond the recognition of these short consensus DNA sequences. These factors include DNA methylation, chromatin structure, posttranslational modifications of transcription factors, and the cooperative recruitment of transcription factor complexes. Chromatin immunoprecipitation (ChIP) provides a means of isolating transcription factor complexes in the context of endogenous chromatin, allowing the identification of direct transcription factor targets. ChIP can be combined with site-specific PCR for candidate binding sites or alternatively with cloning, genomic microarrays or more recently direct high throughput sequencing to identify novel genomic targets. The application of ChIP-based approaches has redefined consensus binding motifs for transcription factors and provided important insights into transcription factor biology.

Mapping Protein-DNA Interactions Using ChIP-exo and Illumina-Based Sequencing

Chromatin immunoprecipitation (ChIP) provides a means of enriching DNA associated with transcription factors, histone modifications, and indeed any other proteins for which suitably characterized antibodies are available. Over the years, sequence detection has progressed from quantitative real-time PCR and Southern blotting to microarrays (ChIP-chip) and now high-throughput sequencing (ChIP-seq). This progression has vastly increased the sequence coverage and data volumes generated. This in turn has enabled informaticians to predict the identity of multi-protein complexes on DNA based on the overrepresentation of sequence motifs in DNA enriched by ChIP with a single antibody against a single protein. In the course of the development of high-throughput sequencing, little has changed in the ChIP methodology until recently. In the last three years, a number of modifications have been made to the ChIP protocol with the goal of enhancing the sensitivity of the method and further reducing the levels of nonspecific background sequences in ChIPped samples. In this chapter, we provide a brief commentary on these methodological changes and describe a detailed ChIP-exo method able to generate narrower peaks and greater peak coverage from ChIPped material.

Generic SoC QR Array Processor for Adaptive Beamforming

A generic architecture for implementing a QR array processor in silicon is presented. This improves on previous research by considerably simplifying the derivation of timing schedules for a QR system implemented as a folded linear array, where account has to be taken of processor cell latency and timing at the detailed circuit level. The architecture and scheduling derived have been used to create a generator for the rapid design of System-on-a-Chip (SoC) cores for QR decomposition. This is demonstrated through the design of a single-chip architecture for implementing an adaptive beamformer for radar applications. Published as IEEE Trans Circuits and Systems Part II, Analog and Digital Signal Processing, April 2003 NOT Express Briefs. Parts 1 and II of Journal reorganised since then into Regular Papers and Express briefs

Reuseable Silicon IP Cores for Discrete Wavelet Transform Applications

Architectures and methods for the rapid design of silicon cores for implementing discrete wavelet transforms over a wide range of specifications are described. These architectures are efficient, modular, scalable, and cover orthonormal and biorthogonal wavelet transform families. They offer efficient hardware utilization by exploiting a number of core wavelet filter properties and allow the creation of silicon designs that are highly parameterized, including in terms of wavelet type and wordlengths. Control circuitry is embedded within these systems allowing them to be cascaded for any desired level of decomposition without any interface glue logic. The time to produce chip designs for a specific wavelet application is typically less than a day and these are comparable in area and performance to handcrafted designs. They are also portable across a wide range of silicon foundries and suitable for field programmable gate array and programmable logic data implementation. The approach described has also been extended to wavelet packet transforms.

Field configured assembly: Programmed manipulation and self-assembly at the mesoscale

Field configured assembly is a programmable force field method that permits rapid, "hands-free" manipulation, assembly, and integration of mesoscale objects and devices. In this method, electric fields, configured by specific addressing of receptor and counter electrode sites pre-patterned at a silicon chip substrate, drive the field assisted transport, positioning, and localization of mesoscale devices at selected receptor locations. Using this approach, we demonstrate field configured deterministic and stochastic self-assembly of model mesoscale devices, i.e., 50 mum diameter, 670 nm emitting GaAs-based light emitting diodes, at targeted receptor sites on a silicon chip. The versatility of the field configured assembly method suggests that it is applicable to self-assembly of a wide variety of functionally integrated nanoscale and mesoscale systems.