Rotman lens based-retrodirective array

A new type of broadband retrodirective array, which has been constructed using a microstrip Rotman lens, is presented. Automatic tracking of targets is obtained by exploiting the conjugate phase response of the beamforming network which is exhibited when the input ports are terminated with either open or short circuits. In addition, the true time-delay property of the Rotman lens gives broadband operation of the self-tracking array when used in conjunction with Vivaldi antennas. The simulated and measured bistatic and monostatic radar cross-section (RCS) patterns of a structure consisting of 13 beamports and 12 array ports are presented at frequencies in the range 8-12 GHz. Significantly enhanced RCS within the scan coverage ±40° is demonstrated by comparing the retrodirective behavior of a 12-element Vivaldi array terminated with and without the Rotman lens. © 2006 IEEE.

Generation of a train of ultrashort pulses from a compact birefringent crystal array

A linear array of n calcite crystals is shown to allow the generation of a high contrast (> 10: 1) train of 2(n) high energy (> 100 mu J) pulses from a single ultrafast laser pulse. Advantage is taken of the pulse-splitting properties of a single birefringent crystal, where an incident laser pulse can be split into two pulses with orthogonal polarizations and equal intensity, separated temporally in proportion to the thickness of the crystal traversed and the difference in refractive indices of the two optic axes. In the work presented here an array of seven calcite crystals of sequentially doubled thickness is used to produce a train of 128 pulses, each of femtosecond duration. Readily versatile properties such as the number of pulses in the train and variable mark-space ratio are realized from such a setup. (c) 2007 Optical Society of America

YIELD ENHANCEMENT OF BIT LEVEL SYSTOLIC ARRAY CHIPS USING FAULT TOLERANT TECHNIQUES.

Methods by which bit level systolic array chips can be made fault tolerant are discussed briefly. Using a simple analysis based on both Poisson and Bose-Einstein statistics authors demonstrate that such techniques can be used to obtain significant yield enhancement. Alternatively, the dimensions of an array can be increased considerably for the same initial (nonfault tolerant) chip yield.

OPTIMISED BIT LEVEL SYSTOLIC ARRAY FOR CONVOLUTION.

A bit level systolic array for computing the convolution operation is described. The circuit in question is highly regular and ideally suited to VLSI chip design. It is also optimized in the sense that all the cells contribute to the computation on each clock cycle. This makes the array almost four times more efficient than one which was previously described.

SOME SYSTOLIC ARRAY DEVELOPMENTS IN THE UNITED KINGDOM.

Two major UK systolic array projects are described. The first concerns the development of a wavefront array processor for adaptive beamforming; the second concerns the design of bit-level systolic arrays for high-performance signal processing.

USE OF UNIDIRECTIONAL DATA FLOW IN BIT-LEVEL SYSTOLIC ARRAY CHIPS.

We show how the architecture of two recently reported bit-level systolic array circuits - a single-bit coefficient correlator and a multibit convolver - may be modified to incorporate unidirectional data flow. This feature has advantages in terms of chip cascadability, fault tolerance and possible wafer-scale integration.

COMPLETELY ITERATIVE, PIPELINED MULTIPLIER ARRAY SUITABLE FOR VLSI.

A pipelined array multiplier which has been derived by applying 'systolic array' principles at the bit level is described. Attention is focused on a circuit which is used to multiply streams of parallel unsigned data. Then an algorithm is given which demonstrates that, with only a simple modification to the basic cell, the same array can cope with two's complement numbers. The resulting structure has a number of features whch make it attractive to LSI and VLSI. These include regularity and modularity.

BIT-LEVEL SYSTOLIC ARRAY CIRCUIT FOR MATRIX VECTOR MULTIPLICATION.

A bit-level systolic array for computing matrix x vector products is described. The operation is carried out on bit parallel input data words and the basic circuit takes the form of a 1-bit slice. Several bit-slice components must be connected together to form the final result, and authors outline two different ways in which this can be done. The basic array also has considerable potential as a stand-alone device, and its use in computing the Walsh-Hadamard transform and discrete Fourier transform operations is briefly discussed.

Automated design of DSP array processor chips

Details are presented of the DAC (DSP ASIC Compiler) silicon compiler framework. DAC allows a non-specialist to automatically design DSP ASICs and DSP ASIC cores directly form a high level specification. Typical designs take only several minutes and the resulting layouts are comparable in area and performance to handcrafted designs.