Systemic psychotherapy as an intervention for post-traumatic stress responses: an introduction, theoretical rationale and overview of developments in an emerging field of interest

The purpose of this article is to critically examine the literature to provide a rationale for including systemic family therapy (SFT) in the psycho-social treatment of people suffering the impact of post-traumatic stress (PTS). Attention is drawn to the relatively underdeveloped academic literature on PTS and the family. The impact of PTS is conceptualized within a psycho-social framework and the current evidence base for psycho-social interventions for PTS responses is described, highlighting the opportunity and need to undergird this area of daily practice. The impact of PTS on the family at multiple levels is identified, emphasizing its recursive nature. The case for SFT is articulated and a range of models of family intervention for PTS briefly reviewed, concluding with an emphasis on Walsh's key processes in family resilience as a framework for practice.

Reasoning about orchestrations of web services using partial correctness

A service is a remote computational facility which is made available for general use by means of a wide-area network. Several types of service arise in practice: stateless services, shared state services and services with states which are customised for individual users. A service-based orchestration is a multi-threaded computation which invokes remote services in order to deliver results back to a user (publication). In this paper a means of specifying services and reasoning about the correctness of orchestrations over stateless services is presented. As web services are potentially unreliable the termination of even finite orchestrations cannot be guaranteed. For this reason a partial-correctness powerdomain approach is proposed to capture the semantics of recursive orchestrations.

A hardware solution on multi-field packet classification

In this paper, a hardware solution for packet classification based on multi-fields is presented. The proposed scheme focuses on a new architecture based on the decomposition method. A hash circuit is used in order to reduce the memory space required for the Recursive Flow Classification (RFC) algorithm. The implementation results show that the proposed architecture achieves significant performance advantage that is comparable to that of some well-known algorithms. The solution is based on Altera Stratix III FPGA technology.

From bit level systolic arrays to HDTV processor chips

The initial part of this paper reviews the early challenges (c 1980) in achieving real-time silicon implementations of DSP computations. In particular, it discusses research on application specific architectures, including bit level systolic circuits that led to important advances in achieving the DSP performance levels then required. These were many orders of magnitude greater than those achievable using programmable (including early DSP) processors, and were demonstrated through the design of commercial digital correlator and digital filter chips. As is discussed, an important challenge was the application of these concepts to recursive computations as occur, for example, in Infinite Impulse Response (IIR) filters. An important breakthrough was to show how fine grained pipelining can be used if arithmetic is performed most significant bit (msb) first. This can be achieved using redundant number systems, including carry-save arithmetic. This research and its practical benefits were again demonstrated through a number of novel IIR filter chip designs which at the time, exhibited performance much greater than previous solutions. The architectural insights gained coupled with the regular nature of many DSP and video processing computations also provided the foundation for new methods for the rapid design and synthesis of complex DSP System-on-Chip (SoC), Intellectual Property (IP) cores. This included the creation of a wide portfolio of commercial SoC video compression cores (MPEG2, MPEG4, H.264) for very high performance applications ranging from cell phones to High Definition TV (HDTV). The work provided the foundation for systematic methodologies, tools and design flows including high-level design optimizations based on "algorithmic engineering" and also led to the creation of the Abhainn tool environment for the design of complex heterogeneous DSP platforms comprising processors and multiple FPGAs. The paper concludes with a discussion of the problems faced by designers in developing complex DSP systems using current SoC technology. © 2007 Springer Science+Business Media, LLC.

SYSTOLIC IIR FILTERS WITH BIT LEVEL PIPELINING.

A novel bit-level systolic array architecture for implementing first-order IIR filter sections is presented. A latency of only two clock cycles is achieved by using a radix-4 redundant number representation, performing the recursive computation most-significant-digit first, and feeding back each digit of the result as soon as it is available.

Bit-level systolic architecture for very high performance IIR filters

A novel bit-level systolic array architecture for implementing bit-parallel IIR filter sections is presented. The authors have shown previously how the fundamental obstacle of pipeline latency in recursive structures can be overcome by the use of redundant arithmetic in combination with bit-level feedback. These ideas are extended by optimizing the degree of redundancy used in different parts of the circuit and combining redundant circuit techniques with those of conventional arithmetic. The resultant architecture offers significant improvements in hardware complexity and throughput rate.

Bit-level systolic arrays for IIR filtering.

A novel bit-level systolic array architecture for implementing IIR (infinite-impulse response) filter sections is presented. A first-order section achieves a latency of only two clock cycles by using a radix-2 redundant number representation, performing the recursive computation most significant digit first, and feeding back each digit of the result as soon as it is available. The design is extended to produce a building block from which second- and higher-order sections can be connected.

Systolic two-port adaptor for high performance wave digital filtering

The authors present a VLSI circuit for implementing wave digital filter (WDF) two-port adaptors. Considerable speedups over conventional designs have been obtained using fine grained pipelining. This has been achieved through the use of most significant bit (MSB) first carry-save arithmetic, which allows systems to be designed in which latency L is small and independent of either coefficient or input data wordlength. L is determined by the online delay associated with the computation required at each node in the circuit (in this case a multiply/add plus two separate additions). This in turn means that pipelining can be used to considerably enhance the sampling rate of a recursive digital filter. The level of pipelining which will offer enhancement is determined by L and is fine-grained rather than bit level. In the case of the circuit considered, L = 3. For this reason pipeline delays (half latches) have been introduced between every two rows of cells to produce a system with a once every cycle sample rate.

Kernel-based local order estimation of nonlinear nonparametric systems

We consider the local order estimation of nonlinear autoregressive systems with exogenous inputs (NARX), which may have different local dimensions at different points. By minimizing the kernel-based local information criterion introduced in this paper, the strongly consistent estimates for the local orders of the NARX system at points of interest are obtained. The modification of the criterion and a simple procedure of searching the minimum of the criterion, are also discussed. The theoretical results derived here are tested by simulation examples.

An integrated approach for real-time model-based state-of-charge estimation of lithium-ion batteries

Lithium-ion batteries have been widely adopted in electric vehicles (EVs), and accurate state of charge (SOC) estimation is of paramount importance for the EV battery management system. Though a number of methods have been proposed, the SOC estimation for Lithium-ion batteries, such as LiFePo4 battery, however, faces two key challenges: the flat open circuit voltage (OCV) vs SOC relationship for some SOC ranges and the hysteresis effect. To address these problems, an integrated approach for real-time model-based SOC estimation of Lithium-ion batteries is proposed in this paper. Firstly, an auto-regression model is adopted to reproduce the battery terminal behaviour, combined with a non-linear complementary model to capture the hysteresis effect. The model parameters, including linear parameters and non-linear parameters, are optimized off-line using a hybrid optimization method that combines a meta-heuristic method (i.e., the teaching learning based optimization method) and the least square method. Secondly, using the trained model, two real-time model-based SOC estimation methods are presented, one based on the real-time battery OCV regression model achieved through weighted recursive least square method, and the other based on the state estimation using the extended Kalman filter method (EKF). To tackle the problem caused by the flat OCV-vs-SOC segments when the OCV-based SOC estimation method is adopted, a method combining the coulombic counting and the OCV-based method is proposed. Finally, modelling results and SOC estimation results are presented and analysed using the data collected from LiFePo4 battery cell. The results confirmed the effectiveness of the proposed approach, in particular the joint-EKF method.

A floating point CORDIC based SVD processor

An SVD processor system is presented in which each processing element is implemented using a simple CORDIC unit. The internal recursive loop within the CORDIC module is exploited, with pipelining being used to multiplex the two independent micro-rotations onto a single CORDIC processor. This leads to a high performance and efficient hardware architecture. In addition, a novel method for scale factor correction is presented which only need be applied once at the end of the computation. This also reduces the computation time. The net result is an SVD architecture based on a conventional CORDIC approach, which combines high performance with high silicon area efficiency.

Two-Stage Orthogonal Least Squares Methods for Neural Network Construction

A number of neural networks can be formulated as the linear-in-the-parameters models. Training such networks can be transformed to a model selection problem where a compact model is selected from all the candidates using subset selection algorithms. Forward selection methods are popular fast subset selection approaches. However, they may only produce suboptimal models and can be trapped into a local minimum. More recently, a two-stage fast recursive algorithm (TSFRA) combining forward selection and backward model refinement has been proposed to improve the compactness and generalization performance of the model. This paper proposes unified two-stage orthogonal least squares methods instead of the fast recursive-based methods. In contrast to the TSFRA, this paper derives a new simplified relationship between the forward and the backward stages to avoid repetitive computations using the inherent orthogonal properties of the least squares methods. Furthermore, a new term exchanging scheme for backward model refinement is introduced to reduce computational demand. Finally, given the error reduction ratio criterion, effective and efficient forward and backward subset selection procedures are proposed. Extensive examples are presented to demonstrate the improved model compactness constructed by the proposed technique in comparison with some popular methods.

Synchrophasor-Based Islanding Detection for Distributed Generation Systems Using Systematic Principal Component Analysis Approaches

Systematic principal component analysis (PCA) methods are presented in this paper for reliable islanding detection for power systems with significant penetration of distributed generations (DGs), where synchrophasors recorded by Phasor Measurement Units (PMUs) are used for system monitoring. Existing islanding detection methods such as Rate-of-change-of frequency (ROCOF) and Vector Shift are fast for processing local information, however with the growth in installed capacity of DGs, they suffer from several drawbacks. Incumbent genset islanding detection cannot distinguish a system wide disturbance from an islanding event, leading to mal-operation. The problem is even more significant when the grid does not have sufficient inertia to limit frequency divergences in the system fault/stress due to the high penetration of DGs. To tackle such problems, this paper introduces PCA methods for islanding detection. Simple control chart is established for intuitive visualization of the transients. A Recursive PCA (RPCA) scheme is proposed as a reliable extension of the PCA method to reduce the false alarms for time-varying process. To further reduce the computational burden, the approximate linear dependence condition (ALDC) errors are calculated to update the associated PCA model. The proposed PCA and RPCA methods are verified by detecting abnormal transients occurring in the UK utility network.

Integrin genetic variants and stage-specific tumor recurrence in patients with stage II and III colon cancer

Integrins (ITGs) are key elements in cancer biology, regulating tumor growth, angiogenesis and lymphangiogenesis through interactions of the tumor cells with the microenvironment. Moving from the hypothesis that ITGs could have different effects in stage II and III colon cancer, we tested whether a comprehensive panel of germline single-nucleotide polymorphisms (SNPs) in ITG genes could predict stage-specific time to tumor recurrence (TTR). A total of 234 patients treated with 5-fluorouracil-based chemotherapy at the University of Southern California were included in this study. Whole-blood samples were analyzed for germline SNPs in ITG genes using PCR-restriction fragment length polymorphism or direct DNA sequencing. In the multivariable analysis, stage II colon cancer patients with at least one G allele for ITGB3 rs4642 had higher risk of recurrence (hazard ratio (HR)=4.027, 95% confidence interval (95% CI) 1.556-10.421, P=0.004). This association was also significant in the combined stage II-III cohort (HR=1.975, 95% CI 1.194-3.269, P=0.008). The predominant role of ITGB3 rs4642 in stage II diseases was confirmed using recursive partitioning, showing that ITGB3 rs4642 was the most important factor in stage II diseases. In contrast, in stage III diseases the combined analysis of ITGB1 rs2298141 and ITGA4 rs7562325 allowed to identify three distinct prognostic subgroups (P=0.009). The interaction between stage and the combined ITGB1 rs2298141 and ITGA4 rs7562325 on TTR was significant (P=0.025). This study identifies germline polymorphisms in ITG genes as independent stage-specific prognostic markers for stage II and III colon cancer. These data may help to select subgroups of patients who may benefit from ITG-targeted treatments.

Common cancer stem cell gene variants predict colon cancer recurrence

PURPOSE: Recent evidence suggests that cancer stem cells (CSC) are responsible for key elements of colon cancer progression and recurrence. Germline variants in CSC genes may result in altered gene function and/or activity, thereby causing interindividual differences in a patient's tumor recurrence capacity and chemoresistance. We investigated germline polymorphisms in a comprehensive panel of CSC genes to predict time to tumor recurrence (TTR) in patients with stage III and high-risk stage II colon cancer.

EXPERIMENTAL DESIGN: A total of 234 patients treated with 5-fluorouracil-based chemotherapy at the University of Southern California were included in this study. Whole blood samples were analyzed for germline polymorphisms in genes that have been previously associated with colon CSC (CD44, Prominin-1, DPP4, EpCAM, ALCAM, Msi-1, ITGB1, CD24, LGR5, and ALDH1A1) by PCR-RFLP or direct DNA-sequencing.

RESULTS: The minor alleles of CD44 rs8193 C>T, ALCAM rs1157 G>A, and LGR5 rs17109924 T>C were significantly associated with increased TTR (9.4 vs. 5.4 years; HR, 0.51; 95% CI: 0.35-0.93; P = 0.022; 11.3 vs. 5.7 years; HR, 0.56; 95% CI: 0.33-0.94; P = 0.024, and 10.7 vs. 5.7 years; HR, 0.33; 95% CI: 0.12-0.90; P = 0.023, respectively) and remained significant in the multivariate analysis stratified by ethnicity. In recursive partitioning, a specific gene variant profile including LGR5 rs17109924, CD44 rs8193, and ALDH1A1 rs1342024 represented a high-risk subgroup with a median TTR of 1.7 years (HR, 6.71, 95% CI: 2.71-16.63, P < 0.001).

CONCLUSION: This is the first study identifying common germline variants in colon CSC genes as independent prognostic markers for stage III and high-risk stage II colon cancer patients.