A floating point CORDIC based SVD processor
| Contribuinte(s) |
Deprettere, E Bhattacharyya, S Cavallaro, J Darte, A Thiele, L |
|---|---|
| Data(s) |
2003
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| Resumo |
<p>An SVD processor system is presented in which each processing element is implemented using a simple CORDIC unit. The internal recursive loop within the CORDIC module is exploited, with pipelining being used to multiplex the two independent micro-rotations onto a single CORDIC processor. This leads to a high performance and efficient hardware architecture. In addition, a novel method for scale factor correction is presented which only need be applied once at the end of the computation. This also reduces the computation time. The net result is an SVD architecture based on a conventional CORDIC approach, which combines high performance with high silicon area efficiency.</p> |
| Identificador | |
| Idioma(s) |
eng |
| Publicador |
IEEE Computer Society |
| Direitos |
info:eu-repo/semantics/restrictedAccess |
| Fonte |
Liu , Z , Dickson , K & McCanny , J V 2003 , A floating point CORDIC based SVD processor . in E Deprettere , S Bhattacharyya , J Cavallaro , A Darte & L Thiele (eds) , Proceedings. IEEE International Conference on Application-Specific Systems, Architectures, and Processors, 2003 . IEEE Computer Society , LOS ALAMITOS , pp. 194-203 , 14th IEEE International Conference on Application-Specific Systems, Architectures and Processors , THE HAGUE , Netherlands , 24-26 June . DOI: 10.1109/ASAP.2003.1212843 |
| Tipo |
contributionToPeriodical |
