Analysis of the Steady Flow Characteristics Through a Poppet Valve

This paper describes the flow characteristics in the near throat region of a poppet valve under steady flow conditions. An experimental and theoretical procedure was undertaken to determine the total pressure at the assumed throat region of the valve, and also at a downstream location. Experiments of this type can be used to accurately determine the flow performance of a particular induction system. The static pressure recovery was calculated from the near throat region of the valve to the downstream location and was shown to be dependant on valve lift. Total pressure profiles suggest that for this particular induction system, the majority of pressure loss occurs downstream of the valve for lift/diameter ratios up to 0.1, and upstream of the valve for lift/diameter ratios greater than 0.1. Negligible pressure recovery was shown to exist from the cylindrical periphery of the valve head to the downstream location for all valve lifts, indicating that the flow had probably separated completely from the trailing edge of the valve seating face. The calculated discharge coefficients, based on the geometric throat static pressure measurements on the seating face, were in general less than those determined using the downstream static pressure, by as much as 12% in some instances towards the valves lower mass flow rate range.

Reuseable Silicon IP Cores for Discrete Wavelet Transform Applications

Architectures and methods for the rapid design of silicon cores for implementing discrete wavelet transforms over a wide range of specifications are described. These architectures are efficient, modular, scalable, and cover orthonormal and biorthogonal wavelet transform families. They offer efficient hardware utilization by exploiting a number of core wavelet filter properties and allow the creation of silicon designs that are highly parameterized, including in terms of wavelet type and wordlengths. Control circuitry is embedded within these systems allowing them to be cascaded for any desired level of decomposition without any interface glue logic. The time to produce chip designs for a specific wavelet application is typically less than a day and these are comparable in area and performance to handcrafted designs. They are also portable across a wide range of silicon foundries and suitable for field programmable gate array and programmable logic data implementation. The approach described has also been extended to wavelet packet transforms.

WLAN Security Processor

A novel wireless local area network (WLAN) security processor is described in this paper. It is designed to offload security encapsulation processing from the host microprocessor in an IEEE 802.11i compliant medium access control layer to a programmable hardware accelerator. The unique design, which comprises dedicated cryptographic instructions and hardware coprocessors, is capable of performing wired equivalent privacy, temporal key integrity protocol, counter mode with cipher block chaining message authentication code protocol, and wireless robust authentication protocol. Existing solutions to wireless security have been implemented on hardware devices and target specific WLAN protocols whereas the programmable security processor proposed in this paper provides support for all WLAN protocols and thus, can offer backwards compatibility as well as future upgrade ability as standards evolve. It provides this additional functionality while still achieving equivalent throughput rates to existing architectures. © 2006 IEEE.

CORDIC based application-specific instruction set processor for QRD/SVD

An application specific programmable processor (ASIP) suitable for the real-time implementation of matrix computations such as Singular Value and QR Decomposition is presented. The processor incorporates facilities for the issue of parallel instructions and a dual-bus architecture that are designed to achieve high performance. Internally, it uses a CORDIC module to perform arithmetic operations, with pipelining of the internal recursive loop exploited to multiplex the two independent micro-rotations onto a single piece of hardware. The net result is a flexible processing element whose functionality can be changed under program control, which combines high performance with efficient silicon implementation. This is illustrated through the results of a detailed silicon design study and the applications of the techniques to a combined SVD/QRD system.

Hardware Performance Analysis of the SHACAL-2 Encryption Algorithm

A hardware performance analysis of the SHACAL-2 encryption algorithm is presented in this paper. SHACAL-2 was one of four symmetric key algorithms chosen in the New European Schemes for Signatures, Integrity and Encryption (NESSIE) initiative in 2003. The paper describes a fully pipelined encryption SHACAL-2 architecture implemented on a Xilinx Field Programmable Gate Array (FPGA) device that achieves a throughput of over 25 Gbps. This is the fastest private key encryption algorithm architecture currently available. The SHACAL-2 decryption algorithm is also defined in the paper as it was not provided in the NESSIE submission.

Platform-Independent IP Transmission over Wireless Networks: The WINE Approach

First demonstration of a working dynamically configurable architecture for wireless IP networks. The programmable architecture was as result of a European collaboration between Industry and University and was applied to a range of IP wireless networks. The work laid the foundations for subsequent research initiatives (including the UK) into programmable wireless networks as well as influencing future wireless standards (e.g. ITU-T).EU project WINE (Wireless Internet NEtworking), -1999-10028.

The Non-Responsive Receiver Problem in Mobile Ad-hoc Networks

This letter exposed a serious unfairness problem with IEEE 802.11 MAC based Mobile Ad-hoc Networks (MANETs) when operating TCP connections, and identifies the three common factors that contribute to this problem. The work initiated the development of a programmable wireless framework that is subsequently used in a spin-out company (TOM), and by the Telecoms Technology Testing centre in Taiwan(Dr D Chieng).

Field configured assembly: Programmed manipulation and self-assembly at the mesoscale

Field configured assembly is a programmable force field method that permits rapid, "hands-free" manipulation, assembly, and integration of mesoscale objects and devices. In this method, electric fields, configured by specific addressing of receptor and counter electrode sites pre-patterned at a silicon chip substrate, drive the field assisted transport, positioning, and localization of mesoscale devices at selected receptor locations. Using this approach, we demonstrate field configured deterministic and stochastic self-assembly of model mesoscale devices, i.e., 50 mum diameter, 670 nm emitting GaAs-based light emitting diodes, at targeted receptor sites on a silicon chip. The versatility of the field configured assembly method suggests that it is applicable to self-assembly of a wide variety of functionally integrated nanoscale and mesoscale systems.

A k-round Elimination Contention Scheme for WLANs

currently in press. This is the first published attempt to engineer QoS into a contention-based MAC layer protocol. The work was based on a cross-layer approach to providing programmability into wireless LANs. The work arose from an EPSRC grant in the "programmable networks" call, with Philips / STM research in Italy (Dr Melpignano). Subsequent follow-on includes the formation of a spin-out company (TOM) based on the idea.