Image processing chip for small object detection

A new, front-end image processing chip is presented for real-time small object detection. It has been implemented using a 0.6 µ, 3.3 V CMOS technology and operates on 10-bit input data at 54 megasamples per second. It occupies an area of 12.9 mm×13.6 mm (including pads), dissipates 1.5 W, has 92 I/O pins and is to be housed in a 160-pin ceramic quarter flat-pack. It performs both one- and two-dimensional FIR filtering and a multilayer perceptron (MLP) neural network function using a reconfigurable array of 21 multiplication-accumulation cells which corresponds to a window size of 7×3. The chip can cope with images of 2047 pixels per line and can be cascaded to cope with larger window sizes. The chip performs two billion fixed point multiplications and additions per second.

Multiple Luminaire Identification in Airborne Images of Airport’s Approach Lighting Using Mathematical Morphology With Variable Length Structuring Element

The increasing demand for fast air transportation around the clock
has increased the number of night flights in civil aviation over
the past few decades. In night aviation, to land an aircraft, a
pilot needs to be able to identify an airport. The approach
lighting system (ALS) at an airport is used to provide
identification and guidance to pilots from a distance. ALS
consists of more than $100$ luminaires which are installed in a
defined pattern following strict guidelines by the International
Civil Aviation Organization (ICAO). ICAO also has strict
regulations for maintaining the performance level of the
luminaires. However, once installed, to date there is no automated
technique by which to monitor the performance of the lighting. We
suggest using images of the lighting pattern captured using a camera
placed inside an aircraft. Based on the information contained
within these images, the performance of the luminaires has to be
evaluated which requires identification of over $100$ luminaires
within the pattern of ALS image. This research proposes analysis
of the pattern using morphology filters which use a variable
length structuring element (VLSE). The dimension of the VLSE changes
continuously within an image and varies for different images.
A novel
technique for automatic determination of the VLSE is proposed and
it allows successful identification of the luminaires from the
image data as verified through the use of simulated and real data.

OPTIMISED BIT LEVEL SYSTOLIC ARRAY FOR CONVOLUTION.

A bit level systolic array for computing the convolution operation is described. The circuit in question is highly regular and ideally suited to VLSI chip design. It is also optimized in the sense that all the cells contribute to the computation on each clock cycle. This makes the array almost four times more efficient than one which was previously described.

SOME SYSTOLIC ARRAY DEVELOPMENTS IN THE UNITED KINGDOM.

Two major UK systolic array projects are described. The first concerns the development of a wavefront array processor for adaptive beamforming; the second concerns the design of bit-level systolic arrays for high-performance signal processing.

BIT-LEVEL SYSTOLIC ARRAYS FOR SIGNAL AND IMAGE PROCESSING.

This paper describes the design and the architecture of a bit-level systolic array processor. The bit-level systolic array described is directly applicable to a wide range of image processing operations where high performance and throughput are essential. The architecture is illustrated by describing the operation of the correlator and convolver chips which are being developed. The advantage of the system is also discussed.

Bit-level systolic array implementation of the Winograd Fourier transform algorithm

A bit level systolic array system is proposed for the Winograd Fourier transform algorithm. The design uses bit-serial arithmetic and, in common with other systolic arrays, features nearest-neighbor interconnections, regularity and high throughput. The short interconnections in this method contrast favorably with the long interconnections between butterflies required in the FFT. The structure is well suited to VLSI implementations. It is demonstrated how long transforms can be implemented with components designed to perform a short length transform. These components build into longer transforms preserving the regularity and structure of the short length transform design.

Generic scheduling methods for a linear QR array SoC processor

A scheduling method for implementing a generic linear QR array processor architecture is presented. This improves on previous work. It also considerably simplifies the derivation of schedules for a folded linear system, where detailed account has to be taken of processor cell latency. The architecture and scheduling derived provide the basis of a generator for the rapid design of System-on-a-Chip (SoC) cores for QR decomposition.

Programmable image processing chip

A new high performance, programmable image processing chip targeted at video and HDTV applications is described. This was initially developed for image small object recognition but has much broader functional application including 1D and 2D FIR filtering as well as neural network computation. The core of the circuit is made up of an array of twenty one multiplication-accumulation cells based on systolic architecture. Devices can be cascaded to increase the order of the filter both vertically and horizontally. The chip has been fabricated in a 0.6 µ, low power CMOS technology and operates on 10 bit input data at over 54 Megasamples per second. The introduction gives some background to the chip design and highlights that there are few other comparable devices. Section 2 gives a brief introduction to small object detection. The chip architecture and the chip design will be described in detail in the later sections.

A wideband antenna array for DVB-T based passive bistatic radar applications

A Digital Video Broadcast Terrestrial (DVB-T) based passive radar requires the development of an antenna array that performs satisfactorily over the entire DVB-T band. The array should require no mechanical adjustments to inter-element spacing to correspond to the DVB-T carrier frequency used for any particular measurement. This paper will describe the challenges involved in designing an antenna array with a bandwidth of 450 MHz. It will discuss the design procedure and demonstrate a number of simulated array configurations. The final configuration of the array will be shown as well as simulations of the expected performance over the desired frequency span.

Design of a wideband conformal array antenna system with beamforming and null steering, for application in a DVB-T based passive radar

The use of radars in detecting low flying, small targets is being explored for several decades now. However radar with counter-stealth abilities namely the passive, multistatic, low frequency radars are in the focus recently. Passive radar that uses Digital Video Broadcast Terrestrial (DVB-T) signals as illuminator of opportunity is a major contender in this area. A DVB-T based passive radar requires the development of an antenna array that performs satisfactorily over the entire DVB-T band. At Fraunhofer FHR, there is currently a need for an array antenna to be designed for operation over the 450-900 MHz range with wideband beamforming and null steering capabilities. This would add to the ability of the passive radar in detecting covert targets and would improve the performance of the system. The array should require no mechanical adjustments to inter-element spacing to correspond to the DVB-T carrier frequency used for any particular measurement. Such an array would have an increased flexibility of operation in different environment or locations.

The design of such an array antenna and the applied techniques for wideband beamforming and null steering are presented in the thesis. The interaction between the inter-element spacing, the grating lobes and the mutual couplings had to be carefully studied and an optimal solution was to be reached at that meets all the specifications of the antenna array for wideband applications. Directional beams, nulls along interference directions, low sidelobe levels, polarization aspects and operation along a wide bandwidth of 450-900 MHz were some of the key considerations.

You have free access to this content 5.8 GHz full duplex amplitude shift keying retrodirective interrogator array

This article describes a practical demonstration of a complete full-duplex “amplitude shift keying (ASK)” retrodirective radio frequency identification (RFID) transceiver array.The interrogator incorporates a “retrodirective array (RDA)” with a dual-conversion phase conjugating architecture in order to achieve better performance than is possible with conventional RFID solutions. Here mixers phase conjugate the incoming signal and a carrier recovery circuit recovers incoming angle of arrival phase information of an encoded amplitude shift keyed signal. The resulting interrogator provides a receiver sensitivity level of -109 dBm. A four element square patch RDA gives a 3 dB automatic beam steering angle of acceptance of ±45°. When compared to an RFID system operating by conventional (non-retrodirective) means retrodirective action leads to improved range extension of up to 16 times at ±45°. Operator pointing accuracy requirements are also reduced due to automatic retrodirective self-pointing. These features significantly enhance deployment opportunities requiring long range low equivalent isotropic radiation power (EIRP) and/or RFID tagging of moving platforms. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:160–164, 2013; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27258

Performance analysis of an infinite array linear clustered plug nozzle

The effects of module shape, module design, three dimensional flow field generated by modules, and partition of primary nozzle on the performance of an infinite array linear clustered plug nozzle are discussed. The module shape is a critical element for nozzle performance and the partition of the primary nozzle with round-to square modules causes a vacuum thrust reduction with respect to two-dimensional model. The performance analysis of different module configuration allows weighing separately the role of clustering and the role of module design. In operating conditions characterized by turned off modules the performance loss is larger, but the difference due to the module shape are smaller and mostly due to the module contribution. The performance of the plug nozzle can be improved by module design, which reduces the module exit flow nonuniformity.

Effect of the crown design and interface lute parameters on the stress-state of a machined crown-tooth system: A finite element analysis

The effect of preparation design and the physical properties of the interface lute on the restored machined ceramic crown-tooth complex are poorly understood. The aim of this work was to determine, by means of three-dimensional finite element analysis (3D FEA) the effect of the tooth preparation design and the elastic modulus of the cement on the stress state of the cemented machined ceramic crown-tooth complex. The three-dimensional structure of human premolar teeth, restored with adhesively cemented machined ceramic crowns, was digitized with a micro-CT scanner. An accurate, high resolution, digital replica model of a restored tooth was created. Two preparation designs, with different occlusal morphologies, were modeled with cements of 3 different elastic moduli. Interactive medical image processing software (mimics and professional CAD modeling software) was used to create sophisticated digital models that included the supporting structures; periodontal ligament and alveolar bone. The generated models were imported into an FEA software program (hypermesh version 10.0, Altair Engineering Inc.) with all degrees of freedom constrained at the outer surface of the supporting cortical bone of the crown-tooth complex. Five different elastic moduli values were given to the adhesive cement interface 1.8 GPa, 4 GPa, 8 GPa, 18.3 GPa and 40 GPa; the four lower values are representative of currently used cementing lutes and 40 GPa is set as an extreme high value. The stress distribution under simulated applied loads was determined. The preparation design demonstrated an effect on the stress state of the restored tooth system. The cement elastic modulus affected the stress state in the cement and dentin structures but not in the crown, the pulp, the periodontal ligament or the cancellous and cortical bone. The results of this study suggest that both the choice of the preparation design and the cement elastic modulus can affect the stress state within the restored crown-tooth complex.

IPPro: FPGA based Image Processing Processor

The paper presents IPPro which is a high performance, scalable soft-core processor targeted for image processing applications. It has been based on the Xilinx DSP48E1 architecture using the ZYNQ Field Programmable Gate Array and is a scalar 16-bit RISC processor that operates at 526MHz, giving 526MIPS of performance. Each IPPro core uses 1 DSP48, 1 Block RAM and 330 Kintex-7 slice-registers, thus making the processor as compact as possible whilst maintaining flexibility and programmability. A key aspect of the approach is in reducing the application design time and implementation effort by using multiple IPPro processors in a SIMD mode. For different applications, this allows us to exploit different levels of parallelism and mapping for the specified processing architecture with the supported instruction set. In this context, a Traffic Sign Recognition (TSR) algorithm has been prototyped on a Zedboard with the colour and morphology operations accelerated using multiple IPPros. Simulation and experimental results demonstrate that the processing platform is able to achieve a speedup of 15 to 33 times for colour filtering and morphology operations respectively, with a reduced design effort and time.

Multipair Full-Duplex Relaying with Massive Arrays and Linear Processing

We consider a multipair decode-and-forward relay channel, where multiple sources transmit simultaneously their signals to multiple destinations with the help of a full-duplex relay station. We assume that the relay station is equipped with massive arrays, while all sources and destinations have a single antenna. The relay station uses channel estimates obtained from received pilots and zero-forcing (ZF) or maximum-ratio combining/maximum-ratio transmission (MRC/MRT) to process the signals. To reduce significantly the loop interference effect, we propose two techniques: i) using a massive receive antenna array; or ii) using a massive transmit antenna array together with very low transmit power at the relay station. We derive an exact achievable rate in closed-form for MRC/MRT processing and an analytical approximation of the achievable rate for ZF processing. This approximation is very tight, especially for large number of relay station antennas. These closed-form expressions enable us to determine the regions where the full-duplex mode outperforms the half-duplex mode, as well as, to design an optimal power allocation scheme. This optimal power allocation scheme aims to maximize the energy efficiency for a given sum spectral efficiency and under peak power constraints at the relay station and sources. Numerical results verify the effectiveness of the optimal power allocation scheme. Furthermore, we show that, by doubling the number of transmit/receive antennas at the relay station, the transmit power of each source and of the relay station can be reduced by 1.5dB if the pilot power is equal to the signal power, and by 3dB if the pilot power is kept fixed, while maintaining a given quality-of-service.