State detection of bond wires in IGBT modules using eddy current pulsed thermography

Insulated gate bipolar transistor (IGBT) modules are important safety critical components in electrical power systems. Bond wire lift-off, a plastic deformation between wire bond and adjacent layers of a device caused by repeated power/thermal cycles, is the most common failure mechanism in IGBT modules. For the early detection and characterization of such failures, it is important to constantly detect or monitor the health state of IGBT modules, and the state of bond wires in particular. This paper introduces eddy current pulsed thermography (ECPT), a nondestructive evaluation technique, for the state detection and characterization of bond wire lift-off in IGBT modules. After the introduction of the experimental ECPT system, numerical simulation work is reported. The presented simulations are based on the 3-D electromagnetic-thermal coupling finite-element method and analyze transient temperature distribution within the bond wires. This paper illustrates the thermal patterns of bond wires using inductive heating with different wire statuses (lifted-off or well bonded) under two excitation conditions: nonuniform and uniform magnetic field excitations. Experimental results show that uniform excitation of healthy bonding wires, using a Helmholtz coil, provides the same eddy currents on each, while different eddy currents are seen on faulty wires. Both experimental and numerical results show that ECPT can be used for the detection and characterization of bond wires in power semiconductors through the analysis of the transient heating patterns of the wires. The main impact of this paper is that it is the first time electromagnetic induction thermography, so-called ECPT, has been employed on power/electronic devices. Because of its capability of contactless inspection of multiple wires in a single pass, and as such it opens a wide field of investigation in power/electronic devices for failure detection, performance characterization, and health monitoring. 

In situ diagnostics and prognostics of solder fatigue in IGBT modules for electric vehicle drives

This paper proposes an in situ diagnostic and prognostic (D&P) technology to monitor the health condition of insulated gate bipolar transistors (IGBTs) used in EVs with a focus on the IGBTs' solder layer fatigue. IGBTs' thermal impedance and the junction temperature can be used as health indicators for through-life condition monitoring (CM) where the terminal characteristics are measured and the devices' internal temperature-sensitive parameters are employed as temperature sensors to estimate the junction temperature. An auxiliary power supply unit, which can be converted from the battery's 12-V dc supply, provides power to the in situ test circuits and CM data can be stored in the on-board data-logger for further offline analysis. The proposed method is experimentally validated on the developed test circuitry and also compared with finite-element thermoelectrical simulation. The test results from thermal cycling are also compared with acoustic microscope and thermal images. The developed circuitry is proved to be effective to detect solder fatigue while each IGBT in the converter can be examined sequentially during red-light stopping or services. The D&P circuitry can utilize existing on-board hardware and be embedded in the IGBT's gate drive unit.

Thermography-based virtual MPPT scheme for improving PV energy efficiency under partial shading conditions

This paper proposes a new thermography-based maximum power point tracking (MPPT) scheme to address photovoltaic (PV) partial shading faults. Solar power generation utilizes a large number of PV cells connected in series and in parallel in an array, and that are physically distributed across a large field. When a PV module is faulted or partial shading occurs, the PV system sees a nonuniform distribution of generated electrical power and thermal profile, and the generation of multiple maximum power points (MPPs). If left untreated, this reduces the overall power generation and severe faults may propagate, resulting in damage to the system. In this paper, a thermal camera is employed for fault detection and a new MPPT scheme is developed to alter the operating point to match an optimized MPP. Extensive data mining is conducted on the images from the thermal camera in order to locate global MPPs. Based on this, a virtual MPPT is set out to find the global MPP. This can reduce MPPT time and be used to calculate the MPP reference voltage. Finally, the proposed methodology is experimentally implemented and validated by tests on a 600-W PV array. 

Control energy consumption and system performance in vector control of voltage source converters

Power electronics plays an important role in the control and conversion of modern electric power systems. In particular, to integrate various renewable energies using DC transmissions and to provide more flexible power control in AC systems, significant efforts have been made in the modulation and control of power electronics devices. Pulse width modulation (PWM) is a well developed technology in the conversion between AC and DC power sources, especially for the purpose of harmonics reduction and energy optimization. As a fundamental decoupled control method, vector control with PI controllers has been widely used in power systems. However, significant power loss occurs during the operation of these devices, and the loss is often dissipated in the form of heat, leading to significant maintenance effort. Though much work has been done to improve the power electronics design, little has focused so far on the investigation of the controller design to reduce the controller energy consumption (leading to power loss in power electronics) while maintaining acceptable system performance. This paper aims to bridge the gap and investigates their correlations. It is shown a more thoughtful controller design can achieve better balance between energy consumption in power electronics control and system performance, which potentially leads to significant energy saving for integration of renewable power sources.

Central-Tapped Node Linked Modular Fault-Tolerance Topology for SRM Applications

Electric vehicles (EVs) and hybrid electric vehicles (HEVs) can reduce greenhouse gas emissions while switched reluctance motor (SRM) is one of the promising motor for such applications. This paper presents a novel SRM fault-diagnosis and fault-tolerance operation solution. Based on the traditional asymmetric half-bridge topology for the SRM driving, the central tapped winding of the SRM in modular half-bridge configuration are introduced to provide fault-diagnosis and fault-tolerance functions, which are set idle in normal conditions. The fault diagnosis can be achieved by detecting the characteristic of the excitation and demagnetization currents. An SRM fault-tolerance operation strategy is also realized by the proposed topology, which compensates for the missing phase torque under the open-circuit fault, and reduces the unbalanced phase current under the short-circuit fault due to the uncontrolled faulty phase. Furthermore, the current sensor placement strategy is also discussed to give two placement methods for low cost or modular structure. Simulation results in MATLAB/Simulink and experiments on a 750-W SRM validate the effectiveness of the proposed strategy, which may have significant implications and improve the reliability of EVs/HEVs.

An Electric Vehicle Dispatch Module for Demand-Side Energy Participation

The penetration of the electric vehicle (EV) has increased rapidly in recent years mainly as a consequence of advances in transport technology and power electronics and in response to global pressure to reduce carbon emissions and limit fossil fuel consumption. It is widely acknowledged that inappropriate provision and dispatch of EV charging can lead to negative impacts on power system infrastructure. This paper considers EV requirements and proposes a module which uses owner participation, through mobile phone apps and on-board diagnostics II (OBD-II), for scheduled vehicle charging. A multi-EV reference and single-EV real-time response (MRS2R) online algorithm is proposed to calculate the maximum and minimum adjustable limits of necessary capacity, which forms part of decision-making support in power system dispatch. The proposed EV dispatch module is evaluated in a case study and the influence of the mobile app, EV dispatch trending and commercial impact is explored.

High-Performance WSe2 CMOS Technology and Integrated Circuits.

Because of their extraordinary structural and electrical properties, two dimensional materials are currently being pursued for applications such as thin-film transistors and integrated circuit. One of the main challenges that still needs to be overcome for these applications is the fabrication of air-stable transistors with industry-compatible complementary metal oxide semiconductor (CMOS) technology. In this work, we experimentally demonstrate a novel high performance air-stable WSe2 CMOS technology with almost ideal voltage transfer characteristic, full logic swing and high noise margin with different supply voltages. More importantly, the inverter shows large voltage gain (~38) and small static power (Pico-Watts), paving the way for low power electronic system in 2D materials.

Plasma power measurement and hysteresis in the E-H transition of a rf inductively coupled plasma system

An experimental investigation of the argon plasma behavior near the E-H transition in an inductively coupled Gaseous Electronics Conference reference cell is reported. Electron density and temperature, ion density, argon metastable density, and optical emission measurements have been made as function of input power and gas pressure. When plotted versus plasma power, applied power corrected for coil and hardware losses, no hysteresis is observed in the measured plasma parameter dependence at the E-H mode transition. This suggests that hysteresis in the E-H mode transition is due to ignoring inherent power loss, primarily in the matching system.

Using signed digit arithmetic for low-power multiplication

Hardware implementations of arithmetic operators using signed digit arithmetic have lost some of their earlier popularity. However, SD is revisited and used to realise an efficient radix-16 generic multiplier, which has particular potential for low-power implementation. The SD multiplier algorithm reduces the number of partial products to as much as 1/4, and in initial tests reduces the estimated power consumption to only about 50% of that of the Booth multiplier. It is different from other previous high-radix methods in that it employs a novel method to generate its partial products with zero arithmetic logic.

Low-power systolic array processor architecture for FSBM video motion estimation

A novel power-efficient systolic array architecture is proposed for full search block matching (FSBM) motion estimation, where the partial distortion elimination algorithm is used to dynamically switch off the computation of eliminated partial candidate blocks. The RTL-level simulation shows that the proposed architecture can reduce the power consumption of the computation part of the algorithm to about 60% of that of the conventional 2D systolic arrays.

Envelope-tracking-based Doherty power amplifier

From the instantaneous efficiency plot, it is observed that the conventional 2-stage Doherty power amplifier (DPA) with high upper power dynamic range (>12 dB) suffers from a substantial dip in the middle of the upper power regime, thus reducing the average efficiency. In this study, an envelope-tracking-based DPA is proposed in order to minimise this dip by adjusting the drain bias voltage of the auxiliary amplifier of the DPA proportional to the input power level.

Improved Direct Power Control of Grid Connected DC/AC Converters

This paper proposes new direct power control (DPC) strategies for three-phase DC/AC converters with improved dynamic response and steady-state performance. As with an electrical machine, source and converter flux which equal the integration of the respective source and converter voltage are used to define active and reactive power flow. Optimization of the look-up-table used in conventional DPC is outlined first, to improve the power control and reduce the current distortion. Then constant switching frequency DPC is developed where the required converter voltage vector within a fixed half switching period is calculated directly from the active and reactive power errors. Detailed angle compensation due to the finite sampling frequency and the use of integral controller to further improve the power control accuracy, are described. Both simulation and experimental results are used to compare conventional DPC and vector control, and to demonstrate the effectiveness and robustness of the proposed control strategies during active and reactive power steps, and line inductance variations.

Randomized caches for power-efficiency

Embedded processors are used in numerous devices executing dedicated applications. This setting makes it worthwhile to optimize the processor to the application it executes, in order to increase its power-efficiency. This paper proposes to enhance direct mapped data caches with automatically tuned randomized set index functions to achieve that goal. We show how randomization functions can be automatically generated and compare them to traditional set-associative caches in terms of performance and energy consumption. A 16 kB randomized direct mapped cache consumes 22% less energy than a 2-way set-associative cache, while it is less than 3% slower. When the randomization function is made configurable (i.e., it can be adapted to the program), the additional reduction of conflicts outweighs the added complexity of the hardware, provided there is a sufficient amount of conflict misses.