Asymptotic modeling of short plane-parallel high-pressure glow discharge

Here a self-consistent continuum model is presented for a narrow gap plane-parallel dc glow discharge. The set of governing equations consisting of continuity and momentum equations for positive ions, fast (emitted by the cathode) and slow electrons (generated by fast electron impact ionization) coupled with Poisson's equation is treated by the technique of matched asymptotic expansions. Explicit results are obtained in the asymptotic limit: (chi delta) much less than 1, where chi = e Phi(a)/kT, delta = (r(D)/L)(2) (Phi(a) is the applied voltage, r(D) is the Debye radius) and pL much greater than 1(Hg mm cm), where p is the gas pressure and L is the gap length. In the case of high pressure, the electron energy relaxation length is much smaller than the gap length, and so the local field approximation is valid. The discharge space divides naturally into a cathode fall sheath, a quasineutral plasma region, and an anode fall sheath. The electric potential distribution obtained for each region in a (semi)analytical form is asymptotically matched to the adjoining regions in the region of overlap. The effects of the gas pressure, gap length, and applied voltage on the length of each region are investigated. (C) 2000 American Institute of Physics. [S1070-664X(00)01302-1].

Parallel Peptidome and Transcriptome Analyses of Amphibian Skin Secretions Using Archived Frozen Acid-Solvated Samples

Amphibian skin secretions are unique sources of bioactive peptides and their donor species are currently rapidly disappearing from the biosphere. Here, we report that both peptides and polyadenylated mRNAs from skin granular glands remain amenable to study in samples of stimulated skin secretions following their storage in 0.1 % aqueous trifluoroacetic acid at -20 °C for many years. Frozen acidified solutions of toad (Bombina variegata) skin secretions, stored for 12 years, were thawed and samples removed for direct reverse phase HPLC fractionation. Additional samples were removed, snap frozen and lyophilised for construction of cDNA libraries following polyadenylated mRNA capture using magnetic oligo-dT beads and reverse transcription. Using the bombesin and bradykinin peptides found in bombinid toad skin as models, individual variant peptides of each type were located in reverse phase HPLC fractions and their corresponding biosynthetic precursor-encoding mRNA transcripts were cloned from the cDNA library using a RACE PCR strategy. This study illustrates unequivocally that both amphibian skin secretion peptides and their biosynthetic precursor-encoding polyadenylated mRNAs are stable in frozen acid-solvated skin secretion samples for considerable periods of time-a finding that may have fundamental implications in the study of archived materials but also in the wider field of molecular biology.

Pull-out behaviour of axially loaded basalt fibre reinforced polymer (BFRP) rods bonded parallel to the grain of glulam elements

Synopsis: Bonded-in rod timber joints off er several advantages over conventional types of joint, including high local force transfer, very stiff connections, and improved ?re and aesthetic properties since the connection is completely hidden in the insulating timber members. More recently, the use of ?bre reinforced polymer (FRP) as a connecting rod, alternative to steel rods, in bonded-in rod connections for timber structures has been investigated. However, the investigation into the behaviour of such joints is limited, in particular, connections involving basalt ?bre reinforced polymers (BFRP) bars - which is the primary focus of this research. This paper presents an experimental programme conducted to investigate the behaviour of bonded-in BFRP bars loaded parallel to the grain of glulam members. Tensile pull-out tests were conducted to examine the effect of bonded length and bond stress-slip on the structural capacity of the connection. An analytical design expression for predicting pull-out capacity is proposed and the results have been compared with some established design equations. It was found that pull-out load increased approximately linearly with the bonded length, up to maximum which occurred at a bonded length of 15 times the hole diameter, and did not increase beyond this bonded length. The most signi?cant failure modes were failure at the timber/adhesive interface followed by pullout of the BFRP rod. Increased bonded lengths resulted in higher bond slip values compared to lower equivalent bonded lengths. The proposed design model gave the best predictions of pull-out capacity compared with other existing models.

A Kernel Interleaved Scheduling Method for Streaming Applications on Soft-core Vector Processors

Massively parallel networks of highly efficient, high performance Single Instruction Multiple Data (SIMD) processors have been shown to enable FPGA-based implementation of real-time signal processing applications with performance and
cost comparable to dedicated hardware architectures. This is achieved by exploiting simple datapath units with deep processing pipelines. However, these architectures are highly susceptible to pipeline bubbles resulting from data and control hazards; the only way to mitigate against these is manual interleaving of
application tasks on each datapath, since no suitable automated interleaving approach exists. In this paper we describe a new automated integrated mapping/scheduling approach to map algorithm tasks to processors and a new low-complexity list scheduling technique to generate the interleaved schedules. When applied to a spatial Fixed-Complexity Sphere Decoding (FSD) detector
for next-generation Multiple-Input Multiple-Output (MIMO) systems, the resulting schedules achieve real-time performance for IEEE 802.11n systems on a network of 16-way SIMD processors on FPGA, enable better performance/complexity balance than current approaches and produce results comparable to handcrafted implementations.

Parallel Programming of General-Purpose Programs Using Task-Based Programming Models

The prevalence of multicore processors is bound to drive most kinds of software development towards parallel programming. To limit the difficulty and overhead of parallel software design and maintenance, it is crucial that parallel programming models allow an easy-to-understand, concise and dense representation of parallelism. Parallel programming models such as Cilk++ and Intel TBBs attempt to offer a better, higher-level abstraction for parallel programming than threads and locking synchronization. It is not straightforward, however, to express all patterns of parallelism in these models. Pipelines are an important parallel construct, although difficult to express in Cilk and TBBs in a straightfor- ward way, not without a verbose restructuring of the code. In this paper we demonstrate that pipeline parallelism can be easily and concisely expressed in a Cilk-like language, which we extend with input, output and input/output dependency types on procedure arguments, enforced at runtime by the scheduler. We evaluate our implementation on real applications and show that our Cilk-like scheduler, extended to track and enforce these dependencies has performance comparable to Cilk++.

A whole-genome massively parallel sequencing analysis of BRCA1 mutant oestrogen receptor-negative and -positive breast cancers

BRCA1 encodes a tumour suppressor protein that plays pivotal roles in homologous recombination (HR) DNA repair, cell-cycle checkpoints, and transcriptional regulation. BRCA1 germline mutations confer a high risk of early-onset breast and ovarian cancer. In more than 80% of cases, tumours arising in BRCA1 germline mutation carriers are oestrogen receptor (ER)-negative; however, up to 15% are ER-positive. It has been suggested that BRCA1 ER-positive breast cancers constitute sporadic cancers arising in the context of a BRCA1 germline mutation rather than being causally related to BRCA1 loss-of-function. Whole-genome massively parallel sequencing of ER-positive and ER-negative BRCA1 breast cancers, and their respective germline DNAs, was used to characterize the genetic landscape of BRCA1 cancers at base-pair resolution. Only BRCA1 germline mutations, somatic loss of the wild-type allele, and TP53 somatic mutations were recurrently found in the index cases. BRCA1 breast cancers displayed a mutational signature consistent with that caused by lack of HR DNA repair in both ER-positive and ER-negative cases. Sequencing analysis of independent cohorts of hereditary BRCA1 and sporadic non-BRCA1 breast cancers for the presence of recurrent pathogenic mutations and/or homozygous deletions found in the index cases revealed that DAPK3, TMEM135, KIAA1797, PDE4D, and GATA4 are potential additional drivers of breast cancers. This study demonstrates that BRCA1 pathogenic germline mutations coupled with somatic loss of the wild-type allele are not sufficient for hereditary breast cancers to display an ER-negative phenotype, and has led to the identification of three potential novel breast cancer genes (ie DAPK3, TMEM135, and GATA4).

UTILISATION OF BIT LEVEL SYSTOLIC ARRAYS IN WORD LEVEL SYSTEMS.

Bit level systolic array structures for computing sums of products are studied in detail. It is shown that these can be sub-divided into two classes and that, within each class, architectures can be described in terms of a set of constraint equations. It is further demonstrated that high performance system level functions with attractive VLSI properties can be constructed by matching data flow geometries in bit level and word level architectures.

Design and test of a bit parallel 2nd order IIR filter structure

Test procedures for a pipelined bit-parallel IIR filter chip which maximally exploit its regularity are described. It is shown that small modifications to the basic architecture result in significant reductions in the number of test patterns required to test such chips. The methods used allow 100% fault coverage to be achieved using less than 1000 test vectors for a chip which has 12 bit data and coefficients.

Systolic array architectures for parameterised multiplexed IIR filters

Whilst conventional bit level pipelining introduces an m cycle delay, it does allow m separate computations to be processed at throughput rates comparable to that using word level systolic arrays. We concentrate on exploiting this delay and describe a systematic method for the design of high performance multiplexed IIR filters. Two multiply and accumulate structures are identified based on shift-and-add and carry-save data organisations which can be used as building blocks in the design of IIR filters. By replacing the word level multiply and accumulate units in word level systolic structures with their equivalent bit level circuits and introducing latches to ensure correct timing, numerous architectures can be designed that process multiplexed data directly without any additional circuit overhead.

Systematic methodology for the design of high performance recursive digital filters

A systematic design methodology is described for the rapid derivation of VLSI architectures for implementing high performance recursive digital filters, particularly ones based on most significant digit (msd) first arithmetic. The method has been derived by undertaking theoretical investigations of msd first multiply-accumulate algorithms and by deriving important relationships governing the dependencies between circuit latency, levels of pipe-lining and the range and number representations of filter operands. The techniques described are general and can be applied to both bit parallel and bit serial circuits, including those based on on-line arithmetic. The method is illustrated by applying it to the design of a number of highly pipelined bit parallel IIR and wave digital filter circuits. It is shown that established architectures, which were previously designed using heuristic techniques, can be derived directly from the equations described.

New algorithms and VLSI architectures for SRT division and square root

In real time digital signal processing, high performance modules for division and square root are essential if many powerful algorithms are to be implemented. In this paper, a new radix 2 algorithms for SRT division and square root are developed. For these new schemes, the result digits and the residuals are computed concurrently and the computations in adjacent rows are overlapped. Consequently, their performance should exceed that of the radix 2 SRT methods. VLSI array architectures to implement the new division and square root schemes are also presented.

Error analysis of FFT architectures for digital video applications

This paper describes how worst-case error analysis can be applied to solve some of the practical issues in the development and implementation of a low power, high performance radix-4 FFT chip for digital video applications. The chip has been fabricated using a 0.6 µm CMOS technology and can perform a 64 point complex forward or inverse FFT on real-time video at up to 18 Megasamples per second. It comprises 0.5 million transistors in a die area of 7.8×8 mm and dissipates 1 W, leading to a cost-effective silicon solution for high quality video processing applications. The analysis focuses on the effect that different radix-4 architectural configurations and finite wordlengths has on the FFT output dynamic range. These issues are addressed using both mathematical error models and through extensive simulation.