Rapid Implementation and Optimisation of DSP Systems on SoPC Heterogeneous Platforms

The emergence of programmable logic devices as processing platforms for digital signal processing applications poses challenges concerning rapid implementation and high level optimization of algorithms on these platforms. This paper describes Abhainn, a rapid implementation methodology and toolsuite for translating an algorithmic expression of the system to a working implementation on a heterogeneous multiprocessor/field programmable gate array platform, or a standalone system on programmable chip solution. Two particular focuses for Abhainn are the automated but configurable realisation of inter-processor communuication fabrics, and the establishment of novel dedicated hardware component design methodologies allowing algorithm level transformation for system optimization. This paper outlines the approaches employed in both these particular instances.

The technical merits of turbogenerating shown through the design, validation and implementation of a 1 dimensional engine model

Turbocompounding is the process of recovering a proportion of an engine’s fuel energy that would otherwise be lost in the exhaust process and adding it to the output power. This was first seen in the 1930s and is carried out by coupling an exhaust gas turbine to the crankshaft of a reciprocating engine. It has since been recognised that coupling the power turbine to an electrical generator instead of the crankshaft has the potential to reduce the fuel consumption further with the added flexibility of being able to decide how this recovered energy is used. The electricity generated can be used in automotive applications to assist the crankshaft using a flywheel motor generator or to power ancillaries that would otherwise have run off the crankshaft. In the case of stationary power plants, it can assist the electrical power output. Decoupling the power turbine from the crankshaft and coupling it to a generator allows the power electronics to control the turbine speed independently in order to optimise the specific fuel consumption for different engine operating conditions. This method of energy recapture is termed ‘turbogenerating’.

This paper gives a brief history of turbocompounding and its thermodynamic merits. It then moves on to give an account of the validation of a turbogenerated engine model. The model is then used to investigate what needs to be done to an engine when a turbogenerator is installed. The engine being modelled is used for stationary power generation and is fuelled by an induced biogas with a small portion of palm oil being injected into the cylinder to initiate combustion by compression ignition. From these investigations, optimum settings were found that result in a 10.90% improvement in overall efficiency. These savings relate to the same engine without a turbogenerator installed operating with fixed fuelling.

Service user involvement in drug treatment programs: Barriers to implementation and potential benefits for client recovery

Service user forums have the potential for improving awareness of services, empowering service users and strengthening community partnerships within an inclusive treatment and rehabilitation framework. The research aimed to investigate perspectives about service user involvement in order to inform the development of effective service user forum(s) in west Ireland. A total of 30 interviews with key service providers and 12 interviews with service users were conducted, with interview questions focusing on: (1) awareness of the Service User Support Team and (2) barriers to service user involvement and the development of service user forums in the region. An integrated data collection and thematic analysis was undertaken. Current levels of service user involvement were low, restricted by one-way communication and appeared grounded in user-provider power differentials and stigma relating to drug dependency. Service providers queried the actual terms of reference, capacity and training that would be needed for service user forums to advocate and lobby for service users. The use of existing support groups, creation of internet user forums and rotation of rural meetings were recommended to promote engagement among service users. The research underscores the need for transparency, resources and a framework for good practice that reflects a participatory approach


Read More: http://informahealthcare.com/doi/abs/10.3109/09687637.2012.671860

IMPLEMENTATION OF SIGNAL PROCESSING FUNCTIONS USING 1-BIT SYSTOLIC ARRAYS.

The use of systolic arrays of 1-bit cells to implement a range of important signal processing functions is demonstrated. Two examples, a pipelined multiplier and a pipelined bit-slice transform circuit, are given. This approach has many important implications for silicon technology, and these are outlined.

COMPLETELY ITERATIVE, PIPELINED MULTIPLIER ARRAY SUITABLE FOR VLSI.

A pipelined array multiplier which has been derived by applying 'systolic array' principles at the bit level is described. Attention is focused on a circuit which is used to multiply streams of parallel unsigned data. Then an algorithm is given which demonstrates that, with only a simple modification to the basic cell, the same array can cope with two's complement numbers. The resulting structure has a number of features whch make it attractive to LSI and VLSI. These include regularity and modularity.

DESIGNING VLSI SIGNAL PROCESSING CHIPS USING DATA DEPENDENCE GRAPHS.

The highly structured nature of many digital signal processing operations allows these to be directly implemented as regular VLSI circuits. This feature has been successfully exploited in the design of a number of commercial chips, some examples of which are described. While many of the architectures on which such chips are based were originally derived on heuristic basis, there is an increasing interest in the development of systematic design techniques for the direct mapping of computations onto regular VLSI arrays. The purpose of this paper is to show how the the technique proposed by Kung can be readily extended to the design of VLSI signal processing chips where the organisation of computations at the level of individual data bits is of paramount importance. The technique in question allows architectures to be derived using the projection and retiming of data dependence graphs.

High performance VLSI architecture for division and square root

A novel high performance bit parallel architecture to perform square root and division is proposed. Relevant VLSI design issues have been addressed. By employing redundant arithmetic and a semisystolic schedule, the throughput has been made independent of the size of the array.

A VLSI architecture for multiplication, division and square root

A high-performance VLSI architecture to perform combined multiply-accumulate, divide, and square root operations is proposed. The circuit is highly regular, requires only minimal control, and can be reconfigured for every cycle. The execution time for each operation is the same. The combination of redundancy and pipelining results in a throughput independent of the wordsize of the array. With current CMOS technology, throughput rates in excess of 80 million operations per second are achievable.

A 64-point fourier transform chip for video motion compensation using phase correlation

Details of a new low power fast Fourier transform (FFT) processor for use in digital television applications are presented. This has been fabricated using a 0.6-µm CMOS technology and can perform a 64 point complex forward or inverse FFT on real-time video at up to 18 Megasamples per second. It comprises 0.5 million transistors in a die area of 7.8 × 8 mm and dissipates 1 W. The chip design is based on a novel VLSI architecture which has been derived from a first principles factorization of the discrete Fourier transform (DFT) matrix and tailored to a direct silicon implementation.

High performance VLSI architecture for Wave Digital Filtering

The application of fine grain pipelining techniques in the design of high performance Wave Digital Filters (WDFs) is described. It is shown that significant increases in the sampling rate of bit parallel circuits can be achieved using most significant bit (msb) first arithmetic. A novel VLSI architecture for implementing two-port adaptor circuits is described which embodies these ideas. The circuit in question is highly regular, uses msb first arithmetic and is implemented using simple carry-save adders. © 1992 Kluwer Academic Publishers.

VLSI module for high-performance multiply, square root and divide

A high-performance VLSI architecture to perform multiply-accumulate, division and square root operations is proposed. The circuit is highly regular, requires only minimal control and can be pipelined right down to the bit level. The system can also be reconfigured on every cycle to perform any one of these operations. The gate count per row has been estimated at (27n+70) gate equivalents where n is the divisor wordlength. The throughput rate, which equals the clock speed, is the same for each operation and is independent of the wordlength. This is achieved through the combination of pipelining and redundant arithmetic. With a 1.0 µm CMOS technology and extensive pipelining, throughput rates in excess of 70 million operations per second are expected.

VLSI architectures for digital image coding

A number of high-performance VLSI architectures for real-time image coding applications are described. In particular, attention is focused on circuits for computing the 2-D DCT (discrete cosine transform) and for 2-D vector quantization. The former circuits are based on Winograd algorithms and comprise a number of bit-level systolic arrays with a bit-serial, word-parallel input. The latter circuits exhibit a similar data organization and consist of a number of inner product array circuits. Both circuits are highly regular and allow extremely high data rates to be achieved through extensive use of parallelism.

Discrete cosine transform generator for VLSI synthesis

A generator for the automated design of Discrete Cosine Transform (DCT) cores is presented. This can be used to rapidly create silicon circuits from a high level specification. These compare very favourably with existing designs. The DCT cores produced are scaleable in terms of point size as well as input/output and coefficient wordlengths. This provides a high degree of flexibility. An example, 8-point 1D DCT design, produced occupies less than 0.92 mm when implemented in a 0.35µ double level metal CMOS technology. This can be clocked at a rate of 100MHz.