Isolation basin records of late Quaternary sea-level change, central mainland British Columbia, Canada.

Isolation basin records from the Seymour-Belize Inlet Complex, a remote area of central mainland British Columbia, Canada are used to constrain post-glacial sea-level changes and provide a preliminary basis for testing geophysical model predictions of relative sea-level (RSL) change. Sedimentological and diatom data from three low-lying (<4 m elevation) basins record falling RSLs in late-glacial times and isolation from the sea by ~11,800–11,200 14C BP. A subsequent RSL rise during the early Holocene (~8000 14C BP) breached the 2.13 m sill of the lowest basin (Woods Lake), but the two more elevated basins (sill elevations of ~3.6 m) remained isolated. At ~2400 14C BP, RSL stood at 1.49 ± 0.34 m above present MTL. Falling RSLs in the late Holocene led to the final emergence of the Woods Lake basin by 1604 ± 36 14C BP. Model predictions generated using the ICE-5G model partnered with a small number of different Earth viscosity models generally show poor agreement with the observational data, indicating that the ice model and/or Earth models considered can be improved upon. The best data-model fits were achieved with relatively low values of upper mantle viscosity (5 × 1019 Pa s), which is consistent with previous modelling results from the region. The RSL data align more closely with observational records from the southeast of the region (eastern Vancouver Island, central Strait of Georgia), than the immediate north (Bella Bella–Bella Coola and Prince Rupert-Kitimat) and areas to the north-west (Queen Charlotte Sound, Hecate Strait), underlining the complexity of the regional response to glacio-isostatic recovery.

Rapid Implementation and Optimisation of DSP Systems on SoPC Heterogeneous Platforms

The emergence of programmable logic devices as processing platforms for digital signal processing applications poses challenges concerning rapid implementation and high level optimization of algorithms on these platforms. This paper describes Abhainn, a rapid implementation methodology and toolsuite for translating an algorithmic expression of the system to a working implementation on a heterogeneous multiprocessor/field programmable gate array platform, or a standalone system on programmable chip solution. Two particular focuses for Abhainn are the automated but configurable realisation of inter-processor communuication fabrics, and the establishment of novel dedicated hardware component design methodologies allowing algorithm level transformation for system optimization. This paper outlines the approaches employed in both these particular instances.

FPGA based Soft-core SIMD Processing: A MIMO-OFDM Fixed-Complexity Sphere Decoder Case Study

To enable reliable data transfer in next generation Multiple-Input Multiple-Output (MIMO) communication systems, terminals must be able to react to fluctuating channel conditions by having flexible modulation schemes and antenna configurations. This creates a challenging real-time implementation problem: to provide the high performance required of cutting edge MIMO standards, such as 802.11n, with the flexibility for this behavioural variability. FPGA softcore processors offer a solution to this problem, and in this paper we show how heterogeneous SISD/SIMD/MIMD architectures can enable programmable multicore architectures on FPGA with similar performance and cost as traditional dedicated circuit-based architectures. When applied to a 4×4 16-QAM Fixed-Complexity Sphere Decoder (FSD) detector we present the first soft-processor based solution for real-time 802.11n MIMO.

Tree-Based Adaptive Spatial Detection for Adaptive Modulated MIMO Systems

Adaptive Multiple-Input Multiple-Output (MIMO) systems achieve a much higher information rate than conventional fixed schemes due to their ability to adapt their configurations according to the wireless communications environment. However, current adaptive MIMO detection schemes exhibit either low performance (and hence low spectral efficiency) or huge computational
complexity. In particular, whilst deterministic Sphere Decoder (SD) detection schemes are well established for static MIMO systems, exhibiting deterministic parallel structure, low computational complexity and quasi-ML detection performance, there are no corresponding adaptive schemes. This paper solves
this problem, describing a hybrid tree based adaptive modulation detection scheme. Fixed Complexity Sphere Decoding (FSD) and Real-Values FSD (RFSD) are modified and combined into a hybrid scheme exploited at low and medium SNR to provide the highest possible information rate with quasi-ML Bit Error
Rate (BER) performance, while Reduced Complexity RFSD, BChase and Decision Feedback (DFE) schemes are exploited in the high SNR regions. This algorithm provides the facility to balance the detection complexity with BER performance with compatible information rate in dynamic, adaptive MIMO communications
environments.

The effects of multiple metal contamination on ectomycorrhizal Scots pine (Pinus sylvestris) seedlings

Experiments were conducted to investigate the effects of single and multiple metal contamination (Cd, Pb, Zn, Sb, Cu) on Scots pine seedlings colonised by ectomycorrhizal (ECM) fungi from natural soil inoculum. Seedlings were grown in either contaminated field soil from the site of a chemical accident, soils amended with five metals contaminating the site, or in soil from an uncontaminated control site. Although contaminated and metal-amended soil significantly inhibited root and shoot growth of the Scots pine seedlings, total root tip density was not affected. Of the five metals tested in amended soils, Cd was the most toxic to ECM Scots pine. Field-contaminated soil had a toxic effect on ECM fungi associated with Scots pine seedlings and caused shifts in ECM species composition on ECM seedlings. When compared to soils amended with only one metal, soils amended with a combination of all five metals tested had lower relative toxicity and less accumulation of Pb, Zn and Sb into seedlings. This would indicate that the toxicity of multiple metal contamination cannot be predicted from the individual toxicity of the metals investigated.

From bit level systolic arrays to HDTV processor chips

The initial part of this paper reviews the early challenges (c 1980) in achieving real-time silicon implementations of DSP computations. In particular, it discusses research on application specific architectures, including bit level systolic circuits that led to important advances in achieving the DSP performance levels then required. These were many orders of magnitude greater than those achievable using programmable (including early DSP) processors, and were demonstrated through the design of commercial digital correlator and digital filter chips. As is discussed, an important challenge was the application of these concepts to recursive computations as occur, for example, in Infinite Impulse Response (IIR) filters. An important breakthrough was to show how fine grained pipelining can be used if arithmetic is performed most significant bit (msb) first. This can be achieved using redundant number systems, including carry-save arithmetic. This research and its practical benefits were again demonstrated through a number of novel IIR filter chip designs which at the time, exhibited performance much greater than previous solutions. The architectural insights gained coupled with the regular nature of many DSP and video processing computations also provided the foundation for new methods for the rapid design and synthesis of complex DSP System-on-Chip (SoC), Intellectual Property (IP) cores. This included the creation of a wide portfolio of commercial SoC video compression cores (MPEG2, MPEG4, H.264) for very high performance applications ranging from cell phones to High Definition TV (HDTV). The work provided the foundation for systematic methodologies, tools and design flows including high-level design optimizations based on "algorithmic engineering" and also led to the creation of the Abhainn tool environment for the design of complex heterogeneous DSP platforms comprising processors and multiple FPGAs. The paper concludes with a discussion of the problems faced by designers in developing complex DSP systems using current SoC technology. © 2007 Springer Science+Business Media, LLC.

64-point Fourier transform chip for digital television applications

A 64-point Fourier transform chip is described that performs a forward or inverse, 64-point Fourier transform on complex two's complement data supplied at a rate of 13.5MHz and can operate at clock rates of up to 40MHz, under worst-case conditions. It uses a 0.6µm double-level metal CMOS technology, contains 535k transistors and uses an internal 3.3V power supply. It has an area of 7.8×8mm, dissipates 0.9W, has 48 pins and is housed in a 84 pin PLCC plastic package. The chip is based on a FFT architecture developed from first principles through a detailed investigation of the structure of the relevant DFT matrix and through mapping repetitive blocks within this matrix onto a regular silicon structure.

High performance VLSI architecture for division and square root

A novel high performance bit parallel architecture to perform square root and division is proposed. Relevant VLSI design issues have been addressed. By employing redundant arithmetic and a semisystolic schedule, the throughput has been made independent of the size of the array.

A 64-point fourier transform chip for video motion compensation using phase correlation

Details of a new low power fast Fourier transform (FFT) processor for use in digital television applications are presented. This has been fabricated using a 0.6-µm CMOS technology and can perform a 64 point complex forward or inverse FFT on real-time video at up to 18 Megasamples per second. It comprises 0.5 million transistors in a die area of 7.8 × 8 mm and dissipates 1 W. The chip design is based on a novel VLSI architecture which has been derived from a first principles factorization of the discrete Fourier transform (DFT) matrix and tailored to a direct silicon implementation.

Systolic building block for high performance recursive filtering

A novel bit level systolic array is presented that can be used as a building block in the construction of recursive digital filters. The circuit accepts bit-parallel input data, is pipelined at the bit level, and exhibits a very high throughput rate. The most important feature of the circuit is that it allows recursive operations to be implemented directly without incurring the large m cycle latency (where m is approximately the word length) normally associated with such systems. The use of this circuit in the construction of both first- and second-order IIR (infinite-impulse-response) filters is described.

Systolic array architectures for parameterised multiplexed IIR filters

Whilst conventional bit level pipelining introduces an m cycle delay, it does allow m separate computations to be processed at throughput rates comparable to that using word level systolic arrays. We concentrate on exploiting this delay and describe a systematic method for the design of high performance multiplexed IIR filters. Two multiply and accumulate structures are identified based on shift-and-add and carry-save data organisations which can be used as building blocks in the design of IIR filters. By replacing the word level multiply and accumulate units in word level systolic structures with their equivalent bit level circuits and introducing latches to ensure correct timing, numerous architectures can be designed that process multiplexed data directly without any additional circuit overhead.