Current-induced transition in atomic-sized contacts of metallic alloys

We have measured conductance histograms of atomic point contacts made from the noble-transition-metal alloys CuNi, AgPd, and AuPt for a concentration ratio of 1:1. For all alloys these histograms at low-bias voltage (below 300 mV) resemble those of the noble metals, whereas at high bias (above 300 mV) they resemble those of the transition metals. We interpret this effect as a change in the composition of the point contact with bias voltage. We discuss possible explanations in terms of electromigration and differential diffusion induced by current heating.

PLL with secondary loop control for self tracking antennas

This paper shows a simple, yet highly effective, tracking phase locked loop circuit which has applications for self steered antenna arrays. The tracking PLL has been demonstrated to accurately phase track signal levels as low as -120 dBm, making it suitable for applications such as SATCOM ground terminals. The implementation is simple requiring a low Q voltage controlled oscillator, a downconverting mixer and a PLL circuit.

High tolerance to gate misalignment in low voltage gate-underlap double gate MOSFETs

.In this letter, we demonstrate for the first time that gate misalignment is not a critical limiting factor for low voltage operation in gate-underlap double gate (DG) devices. Our results show that underlap architecture significantly extends the tolerable limit of gate misalignment in 25 nm devices. DG MOSFETs with high degree of gate misalignment and optimal gate-underlap design can perform comparably or even better than self-aligned nonunderlap devices. Results show that spacer-to-straggle (s/sigma) ratio, a key design parameter for underlap devices, should be within the range of 2.3-3.0 to accommodate back gate misalignment. These results are very significant as the stringent process control requirements for achieving self-alignment in nanoscale planar DG MOSFETs are considerably relaxed

Source/drain extension region engineering in nanoscale double gate SOI MOSFETs: Novel design methodology for low-voltage analog applications

The present paper proposes for the first time, a novel design methodology based on the optimization of source/drain extension (SDE) regions to significantly improve the trade-off between intrinsic voltage gain (A(vo)) and cut-off frequency (f(T)) in nanoscale double gate (DG) devices. Our results show that an optimally designed 25 nm gate length SDE region engineered DG MOSFET operating at drain current of 10 mu A/mu m, exhibits up to 65% improvement in intrinsic voltage gain and 85% in cut-off frequency over devices designed with abrupt SIDE regions. The influence of spacer width, lateral source/drain doping gradient and symmetric as well as asymmetrically designed SDE regions on key analog figures of merit (FOM) such as transconductance (g(m)), transconductance-to-current ratio (g(m)/I-ds), Early voltage (V-EA), output conductance (g(ds)) and gate capacitances are examined in detail. The present work provides new opportunities for realizing future low-voltage/low-power analog circuits with nanoscale SDE engineered DG MOSFETs. (C) 2007 Elsevier B.V. All rights reserved.

Design and optimization of FinFETs for ultra-low-voltage analog applications

In this paper, we analyze the enormous potential of engineering source/drain extension (SDE) regions in FinFETs for ultra-low-voltage (ULV) analog applications. SDE region design can simultaneously improve two key analog figures of merit (FOM)-intrinsic de gain (A(vo)) and cutoff frequency (f(T)) for 60 and 30 nm FinFETs operated at low drive current (J(ds) = 5 mu A/mu m). The improved Avo and fT are nearly twice compared to those of devices with abrupt SDE regions. The influence of the SDE region profile and its impact on analog FOM is extensively analyzed. Results show that SDE region optimization provides an additional degree of freedom apart from device parameters (fin width and aspect ratio) to design future nanoscale analog devices. The results are analyzed in terms of spacer-to-straggle ratio a new design parameter for SDE engineered devices. This paper provides new opportunities for realizing future ULV/low-power analog design with FinFETs.

Source/drain extension region engineering in FinFETs for low-voltage analog applications

In this letter, we propose a novel design methodology for engineering source/drain extension (SDE) regions to simultaneously improve intrinsic dc gain (A(vo)) and cutoff frequency (f(T)) of 25-nm gate-length FinFETs operated at low drain-current (I-ds = 10 mu A/mu m). SDE region optimization in 25-nm FinFETs results in exceptionally high values of Avo (similar to 45 dB) and f(T) (similar to 70 GHz), which is nearly 2.5 times greater when compared to devices designed with abrupt SDE regions. The influence of spacer width, lateral source/drain doping gradient, and the spacer-to-gradient ratio on key analog figures of merit is examined in detail. This letter provides new opportunities for realizing future low-voltage/low-power analog design with nanoscale SDE-engineered FinFETs.

How crucial is back gate misalignment/oversize in double gate MOSFETs for ultra-low-voltage analog/rf applications?

In the present work, by investigating the influence of source/drain (S/D) extension region engineering (also known as gate-underlap architecture) in planar Double Gate (DG) SOI MOSFETs, we offer new design insights to achieve high tolerance to gate misalignment/oversize in nanoscale devices for ultra-low-voltage (ULV) analog/rf applications. Our results show that (i) misaligned gate-underlap devices perform significantly better than DC devices with abrupt source/drain junctions with identical misalignment, (ii) misaligned gate underlap performance (with S/D optimization) exceeds perfectly aligned DG devices with abrupt S/D regions and (iii) 25% back gate misalignment can be tolerated without any significant degradation in cut-off frequency (f(T)) and intrinsic voltage gain (A(VO)). Gate-underlap DG devices designed with spacer-to-straggle ratio lying within the range 2.5 to 3.0 show best tolerance to misaligned/oversize back gate and indeed are better than self-aligned DG MOSFETs with non-underlap (abrupt) S/D regions. Impact of gate length and silicon film thickness scaling is also discussed. These results are very significant as the tolerable limit of misaligned/oversized back gate is considerably extended and the stringent process control requirements to achieve self-alignment can be relaxed for nanoscale planar ULV DG MOSFETs operating in weak-inversion region. The present work provides new opportunities for realizing future ULV analog/rf design with nanoscale gate-underlap DG MOSFETs. (C) 2008 Elsevier Ltd. All rights reserved.

High-efficiency low-voltage-stress Class-EF PA with extended maximum operating frequency

The Class-EF power amplifier (PA) introduced recently has a peak switch voltage much lower than the well-known Class-E PA. However, the value of the transistor output capacitance at high frequencies is typically larger than the required Class-EF optimum shunt capacitance. As a result, softswitching operation that minimizes power dissipation during OFF-to-ON transient cannot be achieved at high frequencies. A novel Class-EF topology with transmission-line load network proposed in this paper allows the PA to operate at much higher frequencies without trading the other figures of merit. Closed-form formulations are derived to simultaneously satisfy the Class-EF impedances requirement at fundamental frequency, all even harmonics, and the first two odd harmonics as well as to provide matching to 50O load. © 2011 Institut fur Mikrowellen.

Process-variation resilient and voltage-scalable dct architecture for robust low-power computing

In this paper, we present a novel discrete cosine transform (DCT) architecture that allows aggressive voltage scaling for low-power dissipation, even under process parameter variations with minimal overhead as opposed to existing techniques. Under a scaled supply voltage and/or variations in process parameters, any possible delay errors appear only from the long paths that are designed to be less contributive to output quality. The proposed architecture allows a graceful degradation in the peak SNR (PSNR) under aggressive voltage scaling as well as extreme process variations. Results show that even under large process variations (±3σ around mean threshold voltage) and aggressive supply voltage scaling (at 0.88 V, while the nominal voltage is 1.2 V for a 90-nm technology), there is a gradual degradation of image quality with considerable power savings (71% at PSNR of 23.4 dB) for the proposed architecture, when compared to existing implementations in a 90-nm process technology. © 2006 IEEE.

Fair charging strategies for EVs connected to a low-voltage distribution network

The development of smart grid technologies and appropriate charging strategies are key to accommodating large numbers of Electric Vehicles (EV) charging on the grid. In this paper a general framework is presented for formulating the EV charging optimization problem and three different charging strategies are investigated and compared from the perspective of charging fairness while taking into account power system constraints. Two strategies are based on distributed algorithms, namely, Additive Increase and Multiplicative Decrease (AIMD), and Distributed Price-Feedback (DPF), while the third is an ideal centralized solution used to benchmark performance. The algorithms are evaluated using a simulation of a typical residential low voltage distribution network with 50% EV penetration. © 2013 IEEE.

Investigation of AIMD based charging strategies for EVs connected to a low-voltage distribution network

In this paper we consider charging strategies that mitigate the impact of domestic charging of EVs on low-voltage distribution networks and which seek to reduce peak power by responding to time-ofday pricing. The strategies are based on the distributed Additive Increase and Multiplicative Decrease (AIMD) charging algorithms proposed in [5]. The strategies are evaluated using simulations conducted on a custom OpenDSS-Matlab platform for a typical low voltage residential feeder network. Results show that by using AIMD based smart charging 50% EV penetration can be accommodated on our test network, compared to only 10% with uncontrolled charging, without needing to reinforce existing network infrastructure. © Springer-Verlag Berlin Heidelberg 2013.