A facile method for the synthesis of Au/PEDOT:PSS nanocomposite

In this work, we have successfully synthesized Au nanoparticles (NPs) in situ in PEDOT:PSS deploying a room temperature atmospheric pressure microplasma. The size of the AuNPs is a function of the gold salt precursor concentration and the plasma processing time. The Au/polymer colloids after processing remain well dispersed over a prolonged period of time. Both gold salt concentration and the plasma processing time have influence on the electrical conductivity of the dried Au/PEDOT:PSS nanocomposite films. An enhanced electrical conductivity of the Au/PEDOT:PSS nanocomposite films has been attributed to (i) the interfacial ligand formation between the S atoms in PEDOT:PSS molecules and the Au surface and (ii) charge transfer from the AuNPs to the holes of PEDOT:PSS molecules.

Atmospheric Pressure DC Plasma Processing of TIO2/PEDOT:PSS Nanocomposites

In this work we demonstrate the synthesis of a TiO2/PEDOT:PSS nanocomposite material in aqueous solution through atmospheric pressure direct current (DC) plasma processing at room temperature. The dispersion of the TiO2 nanoparticles is enhanced after microplasma processing, and TiO2/polymer hybrid nanoparticles with a distinct core shell structure have been obtained. We have observed increased TiO2/PEDOT:PSS nanocomposite electrical conductivity due to microplasma processing. The improvement in nanocomposite properties is due to the enhanced dispersion and stability in liquid polymer of microplasma treated TiO2 nanoparticles. Both plasma induced surface charge and nanoparticle surface termination with specific plasma chemical species are thought to provide an enhanced barrier to nanoparticle agglomeration and promote nanoparticle-polymer bonding, which is expected to have a significant benefit in materials processing with inorganic nanoparticles for wide range of applications.

Enhanced Dispersion of TiO2 Nanoparticles in a TiO2/PEDOT:PSS Hybrid Nanocomposite via Plasma-Liquid Interactions

A facile method to synthesize a TiO2/PEDOT:PSS hybrid nanocomposite material in aqueous solution through direct current (DC) plasma processing at atmospheric pressure and room temperature has been demonstrated. The dispersion of the TiO2 nanoparticles is enhanced and TiO2/polymer hybrid nanoparticles with a distinct core shell structure have been obtained. Increased electrical conductivity was observed for the plasma treated TiO2/PEDOT:PSS nanocomposite. The improvement in nanocomposite properties is due to the enhanced dispersion and stability in liquid polymer of microplasma treated TiO2 nanoparticles. Both plasma induced surface charge and nanoparticle surface termination with specific plasma chemical species are proposed to provide an enhanced barrier to nanoparticle agglomeration and promote nanoparticle-polymer binding.

Analysis and Synthesis of pHEMT Class-E Amplifiers with Shunt Inductor including ON-State Active-Device Resistance Effects

In this theoretical paper, the analysis of the effect that ON-state active-device resistance has on the performance of a Class-E tuned power amplifier using a shunt inductor topology is presented. The work is focused on the relatively unexplored area of design facilitation of Class-E tuned amplifiers where intrinsically low-output-capacitance monolithic microwave integrated circuit switching devices such as pseudomorphic high electron mobility transistors are used. In the paper, the switching voltage and current waveforms in the presence of ON-resistance are analyzed in order to provide insight into circuit properties such as RF output power, drain efficiency, and power-output capability. For a given amplifier specification, a design procedure is illustrated whereby it is possible to compute optimal circuit component values which account for prescribed switch resistance loss. Furthermore, insight into how ON-resistance affects transistor selection in terms of peak switch voltage and current requirements is described. Finally, a design example is given in order to validate the theoretical analysis against numerical simulation.

Parameter sensitivity for optimal design of 65 nm node SOI transistors

Mixed-mode simulation, where device simulation is embedded directly within a circuit simulator, is used for the first time to provide scaling guidelines to achieve optimal digital circuit performance for double gate SOI MOSFETs. This significant advance overcomes the lack of availability of SPICE model parameters. The sensitivity of the gate delay and on-off current ratio to each of the key geometric and technological parameters of the transistor is quantified. The impact of the source-drain doping profile on circuit performance is comprehensively investigated.

Idealised operation of zero-voltage-switching series-L/parallel-tuned Class-E power amplifier

An analysis of a modified series-L/parallel-tuned Class-E power amplifier is presented, which includes the effects that a shunt capacitance placed across the switching device will have on Class-E behaviour. In the original series L/parallel-tuned topology in which the output transistor capacitance is not inherently included in the circuit, zero-current switching (ZCS) and zero-current derivative switching (ZCDS) conditions should be applied to obtain optimum Class-E operation. On the other hand, when the output transistor capacitance is incorporated in the circuit, i.e. in the modified series-L/parallel-tuned topology, the ZCS and ZCDS would not give optimum operation and therefore zero-voltage-switching (ZVS) and zero-voltage-derivative switching (ZVDS) conditions should be applied instead. In the modified series-L/parallel-tuned Class-E configuration, the output-device inductance and the output-device output capacitance, both of which can significantly affect the amplifier's performance at microwave frequencies, furnish part, if not all, of the series inductance L and the shunt capacitance COUT, respectively. Further, when compared with the classic shunt-C/series-tuned topology, the proposed Class-E configuration offers some advantages in terms of 44% higher maximum operating frequency (fMAX) and 4% higher power-output capability (PMAX). As in the classic topology, the fMAX of the proposed amplifier circuit is reached when the output-device output capacitance furnishes all of the capacitance COUT, for a given combination of frequency, output power and DC supply voltage. It is also shown that numerical simulations agree well with theoretical predictions.

Exploring figures of merit associated with the suboptimum operation of class-E power amplifiers

Closed-form design equations for the operation of a class-E amplifier for zero switch voltage slope and arbitrary duty cycle are derived. This approach allows an additional degree of freedom in the design of class-E amplifiers which are normally designed for 50 duty ratio. The analysis developed permits the selection of non-unique solutions where amplifier efficiency is theoretically 100 but power output capability is less than that the 50 duty ratio case would permit. To facilitate comparison between 50 (optimal) and non-50 (suboptimal) duty ratio cases, each important amplifier parameter is normalised to its corresponding optimum operation value. It is shown that by choosing a non-50 suboptimal solution, the operating frequency of a class-E amplifier can be extended. In addition, it is shown that by operating the amplifier in the suboptimal regime, other amplifier parameters, for example, transistor output capacitance or peak switch voltage, can be included along with the standard specification criteria of output power, DC supply voltage and operating frequency as additional input design specifications. Suboptimum class-E operation may have potential advantages for monolithic microwave integrated circuit realisation as lower inductance values (lower series resistance, higher self-resonance frequency, less area) may be required when compared with the results obtained for optimal class-E amplifier synthesis. The theoretical analysis conducted here was verified by harmonic balance simulation, with excellent agreement between both methods. © The Institution of Engineering and Technology 2007.

Optimisation of trench isolated bipolar transistors on SOI substrates by 3D electro-thermal simulations

This paper provides a comprehensive analysis of thermal resistance of trench isolated bipolar transistors on SOI substrates based on 3D electro-thermal simulations calibrated to experimental data. The impact of emitter length, width, spacing and number of emitter fingers on thermal resistance is analysed in detail. The results are used to design and optimise transistors with minimum thermal resistance and minimum transistor area. (c) 2007 Elsevier Ltd. All rights reserved.

6-T SRAM cell design with nanoscale double-gate SOI MOSFETs: impact of source/drain engineering and circuit topology

The impact of source/drain engineering on the performance of a six-transistor (6-T) static random access memory (SRAM) cell, based on 22 nm double-gate (DG) SOI MOSFETs, has been analyzed using mixed-mode simulation, for three different circuit topologies for low voltage operation. The trade-offs associated with the various conflicting requirements relating to read/write/standby operations have been evaluated comprehensively in terms of eight performance metrics, namely retention noise margin, static noise margin, static voltage/current noise margin, write-ability current, write trip voltage/current and leakage current. Optimal design parameters with gate-underlap architecture have been identified to enhance the overall SRAM performance, and the influence of parasitic source/drain resistance and supply voltage scaling has been investigated. A gate-underlap device designed with a spacer-to-straggle (s/sigma) ratio in the range 2-3 yields improved SRAM performance metrics, regardless of circuit topology. An optimal two word-line double-gate SOI 6-T SRAM cell design exhibits a high SNM similar to 162 mV, I-wr similar to 35 mu A and low I-leak similar to 70 pA at V-DD = 0.6 V, while maintaining SNM similar to 30% V-DD over the supply voltage (V-DD) range of 0.4-0.9 V.

Analog performance of double gate SOI transistors

Double gate fully depleted silicon-on-insulator (DGSOI) is recognized as a possible solution when the physical gate length L-G reduces to 25nm for the 65nm node on the ITRS CMOS roadmap. In this paper, scaling guidelines are introduced to optimally design a nanoscale DGSOI. For this reason, the sensitivity of gain, f(T) and f(max) to each of the key geometric and technological parameters of the DGSOI are assessed and quantified using MixedMode simulation. The impact of the parasitic resistance and capacitance on analog device performance is systematically analysed. By comparing analog performance with a single gate (SG), it has been found that intrinsic gain in DGSOI is 4 times higher but its fT was found to be comparable to that of SGSOI at different regions of transistor operation. However, the extracted fmax in SG SOI was higher (similar to 40%) compared to DGSOI due to its lower capacitance.

Synthesis of a neodymium-quinolate complex for near-infrared electroluminescence applications

A structurally pure, near-infrared emissive Nd-(5,7-dichloro-8-hydroxyquinoline)4 tetrakis complex has been synthesized. When incorporated as a dopant in the blue emissive, hole conducting polymer poly(N-vinylcarbazole), PVK, sensitized neodymium ion emission was observed following photo-excitation of the polymer host. OLED devices were fabricated by spin-casting layers of the doped polymer onto glass/indium tin oxide (ITO)/3,4-polyethylene-dioxythiophene-polystyrene sulfonate (PEDOT) substrates. An external quantum efficiency of 1 x 10(-3)% and a near-infrared irradiance of 2.0 nW/mm(2) at 25 mA/mm(2) and 20 V was achieved using glass/ITO/PEDOT/ PVK:Nd-(5,7-dichloro-8-hydroxyquinoline)(4)/Ca/Al devices. (C) 2007 Elsevier B.V. All rights reserved.

Near infrared electroluminescence from neodymium complex-doped polymer light emitting diodes

Organic light emitting diode devices employing organometallic Nd(9-hydroxyphenalen-1-one)(3) complexes as near infrared emissive dopants dispersed within poly(N-vinylcarbazole) (PVK) host matrices have been fabricated by spin-casting layers of the doped polymer onto glass/indium tin oxide (ITO)/3,4-polyethylene-dioxythiophene-polystyrene sulfonate (PEDOT) substrates. Room temperature electroluminescence, centered at similar to 1065 nm. was observed from devices top contacted by evaporated aluminum or calcium metal cathodes and was assigned to transitions between the F-4(3/2) -> I-4(11/2) levels of the Nd3+ ions. In particular, a near infrared irradiance of 8.5 nW/mm(2) and an external quantum efficiency of 0.007% was achieved using glass/ITO/PEDOT/PVK:Nd(9-hydroxyphenalen-1-one)(3)/Ca/Al devices. (c) 2005 Elsevier B.V. All rights reserved.