Medium-Coupled Bus-Based INS-GPS Sensor Fusion for Accurate and Reliable Positioning

A scheme for integration of stand-alone INS and GPS sensors is presented, with data interchange over an external bus. This ensures modularity and sensor interchangeability. Use of a medium-coupled scheme reduces data flow and computation, facilitating use in surface vehicles. Results show that the hybrid navigation system is capable of delivering high positioning accuracy.

Parallel polygon scan conversion algorithms: Performance evaluation on a shared bus architecture

In this paper, three parallel polygon scan conversion algorithms have been proposed, and their performance when executed on a shared bus architecture has been compared. It has been shown that the parallel algorithm that does not use edge coherence performs better than those that use edge coherence. Further, a multiprocessing architecture has been proposed to execute the parallel polygon scan conversion algorithms more efficiently than a single shared bus architecture.

Design and evaluation of a dual-microcomputer shared memory system with a shared I/O bus

The design, implementation and evaluation are described of a dual-microcomputer system based on the concept of shared memory. Shared memory is useful for passing large blocks of data and it also provides a means to hold and work with shared data. In addition to the shared memory, a separate bus between the I/O ports of the microcomputers is provided. This bus is utilized for interprocessor synchronization. Software routines helpful in applying the dual-microcomputer system to realistic problems are presented. Performance evaluation of the system is carried out using benchmarks.

Harmonic Analysis of Advanced Bus-Clamping PWM Techniques

Special switching sequences can be employed in space-vector-based generation of pulsewidth-modulated (PWM) waveforms for voltage-source inverters. These sequences involve switching a phase twice, switching the second phase once, and clamping the third phase in a subcycle. Advanced bus-clamping PWM (ABCPWM) techniques have been proposed recently that employ such switching sequences. This letter studies the spectral properties of the waveforms produced by these PWM techniques. Further, analytical closed-form expressions are derived for the total rms harmonic distortion due to these techniques. It is shown that the ABCPWM techniques lead to lower distortion than conventional space vector PWM and discontinuous PWM at higher modulation indexes. The findings are validated on a 2.2-kW constant $V/f$ induction motor drive and also on a 100-kW motor drive.

Study of voltage collapse at converter bus in asynchronous MTDC-AC systems

This paper presents the analysis and study of voltage collapse at any converter bus in an AC system interconnected by multiterminal DC (MTDC) links. The analysis is based on the use of the voltage sensitivity factor (VSF) as a voltage collapse proximity indicator (VCPI). In this paper the VSF is defined as a matrix which is applicable to MTDC systems. The VSF matrix is derived from the basic steady state equations of the converter, control, DC and AC networks. The structure of the matrix enables the derivation of some of the basic properties which are generally applicable. A detailed case study of a four-terminal MTDC system is presented to illustrate the effects of control strategies at the voltage setting terminal (VST) and other terminals. The controls considered are either constant angle, DC voltage, AC voltage, reactive current and reactive power at the VST and constant power or current at the other terminals. The effect of the strength of the AC system (measured by short circuit ratio) on the VSF is investigated. Several interesting and new results are presented. An analytical expression for the self VSF at VST is also derived for some specific cases which help to explain the number of transitions in VSF around the critical values of SCR.

Common mode DC bus filter for Active Front-End converter

Active Front-End (AFE) converter operation produces electrically noisy DC bus on common mode basis. This results in higher ground current as compared to three phase diode bridge rectifier. Filter topologies for DC bus have to deal problems with switching frequency and harmonic currents. The proposed filter approach reduces common mode voltage and circulates third harmonic current within the system, resulting in minimal ground current injection. The filtering technique, its constrains and design to attenuate common mode voltage and eliminate lower order harmonics injection to ground is discussed. The experimental results for operation of the converter with both SPWM and CSVPWM are presented.

Space vector based bus clamped PWM algorithms for three level inverters: implementation, performance analysis and application considerations

This paper describes the different types of space vector based bus clamped PWM algorithms for three level inverters. A novel bus clamp PWM algorithm for low modulation indices region is also presented. The principles and switching sequences of all the types of bus clamped algorithms for high switching frequency are presented. Synchronized version of the PWM sequences for high power applications where switching frequency is low is also presented. The implementation details on DSP based digital controller and experimental results are presented. The THD of the output waveforms is studied for the entire operating region and is compared with the conventional space vector PWM technique. The bus clamped techniques can be used to reduce the switching losses or to improve the output voltage quality or both.. Different issues dominate depending on the type of application and power rating of the inverters. The results presented in this paper can be used for judicious use of the PWM techniques, which result in improved system efficiency and performance.

Experimental Investigation on the Effect of Advanced Bus-Clamping Pulsewidth Modulation on Motor Acoustic Noise

Voltage source inverters (VSIs) supply nonsinusoidal voltages to induction motor drives, leading to line current distortion and torque pulsation. Conventional space vector pulsewidth modulation (PWM) techniques are widely used in VSIs on the account of good waveform quality and high dc bus utilization. In a conventional space vector PWM technique, the switching sequence begins with one zero state and ends with the other zero state in a subcycle. Some novel switching sequences have been proposed, which employ only one zero state but apply one of the two active states twice in a subcycle. One pair of such special switching sequences has recently been shown to reduce the pulsating torque considerably. In this paper, the conventional and special switching sequences are compared experimentally in terms of acoustic noise. In the low-and medium-speed ranges, the special switching sequence is seen to reduce the amplitude of the tonal component of noise at the switching frequency considerably and is also found to result in spread spectrum.

Study on the Effect of Dead Time and its Compensation for Bus-Clamping PWM Techniques

Dead-time is provided in between the gating signals of the top and bottom semiconductor switches in an inverter leg to prevent the shorting of DC bus. Due to this dead time, there is a significant unwanted change in the output voltage of the inverter. The effect is different for different pulse width modulation (PWM) methodologies. The effect of dead-time on the output fundamental voltage is studied theoretically as well as experimentally for bus-clamping PWM methodologies. Further, experimental observations on the effectiveness of dead-time compensation are presented.

Analysis of the modulation process in advanced bus-clamping PWM techniques

Advanced bus-clamping pulse width modulation (ABCPWM) techniques are advantageous in terms of line current distortion and inverter switching loss in voltage source inverter-fed applications. However, the PWM waveforms corresponding to these techniques are not amenable to carrier-based generation. The modulation process in ABCPWM methods is analyzed here from a “per-phase” perspective. It is shown that three sets of descendant modulating functions (or modified modulating functions) can be generated from the three-phase sinusoidal signals. Each set of the modified modulating functions can be used to produce the PWM waveform of a given phase in a computationally efficient manner. Theoretical results and experimental investigations on a 5hp motor drive are presented

Analytical evaluation of harmonic distortion factor corresponding to generalised advanced bus-clamping pulse width modulation

A few advanced bus-clamping pulse width modulation (ABCPWM) methods have been proposed recently for a three-phase inverter. With these methods, each phase is clamped, switched at nominal frequency, and switched at twice the nominal frequency in different regions of the fundamental cycle. This study proposes a generalised ABCPWM scheme, encompassing the few ABCPWM schemes that have been proposed and many more ABCPWM schemes that have not been reported yet. Furthermore, analytical closed-form expression is derived for the harmonic distortion factor corresponding to the generalised ABCPWM. This factor is independent of load parameters. The analytical expression derived here brings out the dependence of root-mean-square (RMS) current ripple on modulation index, and can be used to evaluate the RMS current ripple corresponding to any ABCPWM scheme. The analytical closed-form expression is validated experimentally in terms of measured weighted total harmonic distortion (THD) in line voltage (V-WTHD) and measured THD in line current (I-THD) on a 6 kW induction motor drive.

Low-frequency dc bus ripple cancellation in single phase pulse-width modulation inverters

This study presents a topology for a single-phase pulse-width modulation (PWM) converter which achieves low-frequency ripple reduction in the dc bus even when there are grid frequency variations. A hybrid filter is introduced to absorb the low-frequency current ripple in the dc bus. The control strategy for the proposed filter does not require the measurement of the dc bus ripple current. The design criteria for selecting the filter components are also presented in this study. The effectiveness of the proposed circuit has been tested and validated experimentally. A smaller dc-link capacitor is sufficient to keep the low-frequency bus ripple to an acceptable range in the proposed topology.

Sampling Period Selection of Control Application Connected to FlexRay Bus

Flexray is a high speed communication protocol designed for distributive control in automotive control applications. Control performance not only depends on the control algorithm but also on the scheduling constraints in communication. A balance between the control performance and communication constraints must required for the choice of the sampling rates of the control loops in a node. In this paper, an optimum sampling period of control loops to minimize the cost function, satisfying the scheduling constraints is obtained. An algorithm to obtain the delay in service of each task in a node of the control loop in the hyper period has been also developed. (C) 2015 The Authors. Published by Elsevier B.V.