Assessment of SET Logic Robustness Through Noise Margin Modeling

A compact model for noise margin (NM) of single-electron transistor (SET) logic is developed, which is a function of device capacitances and background charge (zeta). Noise margin is, then, used as a metric to evaluate the robustness of SET logic against background charge, temperature, and variation of SET gate and tunnel junction capacitances (CG and CT). It is shown that choosing alpha=CT/CG=1/3 maximizes the NM. An estimate of the maximum tolerable zeta is shown to be equal to plusmn0.03 e. Finally, the effect of mismatch in device parameters on the NM is studied through exhaustive simulations, which indicates that a isin [0.3, 0.4] provides maximum robustness. It is also observed that mismatch can have a significant impact on static power dissipation.

'Wet N2O oxidation' process and interface state density characterization of nanoscale nitrided SiO2 for flash memory application

In this paper we first present the 'wet N2O' furnace oxidation process to grow nitrided tunnel oxides in the thickness range 6 to 8 nm on silicon at a temperature of 800 degrees C. Electrical characteristics of MOS capacitors and MOSFETs fabricated using this oxide as gate oxide have been evaluated and the superior features of this oxide are ascertained The frequency response of the interface states, before and after subjecting the MOSFET gate oxide to constant current stress, is studied using a simple analytical model developed in this work.

Necessity for quantum mechanical simulation for the future technology nodes

In this paper we present and compare the results obtained from semi-classical and quantum mechanical simulation for a Double Gate MOSFET structure to analyze the electrostatics and carrier dynamics of this device. The geometries like gate length, body, thickness of this device have been chosen according to the ITRS specification for the different technology nodes. We have shown the extent of deviation between the semi-classical and quantum mechanical results and hence the need of quantum simulations for the promising nanoscale devices in the future technology nodes predicted in ITRS.

Seismic response of reinforced soil retaining wall models: Influence of backfill relative density

This paper presents the results of shaking table tests on model reinforced soil retaining walls in the laboratory. The influence of backfill relative density on the seismic response was studied through a series of laboratory model tests on retaining walls. Construction of model retaining walls in the laminar box mounted on shaking table, instrumentation and results from the shaking table tests are described in detail. Three types of walls: wrap- and rigid-faced reinforced soil walls and unreinforced rigid-faced walls constructed to different densities were tested for a relatively small excitation. Wrap-faced walls are further tested for higher base excitation at different frequencies and relative densities. It is observed from these tests that the effect of backfill density on the seismic performance of reinforced retaining walls is pronounced only at very low relative density and at the higher base excitation. The walls constructed with higher backfill relative density showed lesser face deformations and more acceleration amplifications compared to the walls constructed with lower densities when tested at higher base excitation. The response of wrap- and rigid-faced retaining walls is not much affected by the backfill relative density when tested at smaller base excitation. The effects of facing rigidity were evaluated to a limited extent. Displacements in wrap-faced walls are many times higher compared to rigid-faced walls. The results obtained from this study are helpful in understanding the relative performance of reinforced soil retaining walls constructed to when subjected to smaller and higher base excitation for the range of relative density employed in the testing program. (C) 2007 Elsevier Ltd. All rights reserved.

Process variability-aware statistical hybrid modeling of dynamic power dissipation in 65 nm CMOS designs

A generalized technique is proposed for modeling the effects of process variations on dynamic power by directly relating the variations in process parameters to variations in dynamic power of a digital circuit. The dynamic power of a 2-input NAND gate is characterized by mixed-mode simulations, to be used as a library element for 65mn gate length technology. The proposed methodology is demonstrated with a multiplier circuit built using the NAND gate library, by characterizing its dynamic power through Monte Carlo analysis. The statistical technique of Response. Surface Methodology (RSM) using Design of Experiments (DOE) and Least Squares Method (LSM), are employed to generate a "hybrid model" for gate power to account for simultaneous variations in multiple process parameters. We demonstrate that our hybrid model based statistical design approach results in considerable savings in the power budget of low power CMOS designs with an error of less than 1%, with significant reductions in uncertainty by atleast 6X on a normalized basis, against worst case design.

Design of a high sensitivity FET integrated MEMS microphone

FET based MEMS microphones comprise of a flexible diaphragm that works as the moving gate of the transistor. The integrated electromechanical transducer can be made more sensitive to external sound pressure either by increasing the mechanical or the electrical sensitivities. We propose a method of increasing the overall sensitivity of the microphone by increasing its electrical sensitivity. The proposed microphone uses the transistor biased in the sub-threshold region where the drain current depends exponentially on the difference between the gate-to-source voltage and the threshold voltage. The device is made more sensitive without adding any complexity in the mechanical design of the diaphragm.

Rendering stiffer walls: a hybrid haptic system using continuous and discrete time feedback

Instability in conventional haptic rendering destroys the perception of rigid objects in virtual environments. Inherent limitations in the conventional haptic loop restrict the maximum stiffness that can be rendered. In this paper we present a method to render virtual walls that are much stiffer than those achieved by conventional techniques. By removing the conventional digital haptic loop and replacing it with a part-continuous and part-discrete time hybrid haptic loop, we were able to render stiffer walls. The control loop is implemented as a combinational logic circuit on an field-programmable gate array. We compared the performance of the conventional haptic loop and our hybrid haptic loop on the same haptic device, and present mathematical analysis to show the limit of stability of our device. Our hybrid method removes the computer-intensive haptic loop from the CPU-this can free a significant amount of resources that can be used for other purposes such as graphical rendering and physics modeling. It is our hope that, in the future, similar designs will lead to a haptics processing unit (HPU).

HFinFET: A Scalable, High Performance, Low Leakage Hybrid n-Channel FET

In this letter, we propose the design and simulation study of a novel transistor, called HFinFET, which is a hybrid of an HEMT and a FinFET, to obtain excellent performance and good OFF-state control. Followed by the description of the design, 3-D device simulation has been performed to predict the characteristics of the device. The device has been benchmarked against published state of the art HEMT as well as planar and nonplanar Si n-MOSFET data of comparable gate length using standard benchmarking techniques.

Effect of Li substitution on dielectric and ferroelectric properties of ZnO thin films grown by pulsed-laser ablation

Li-doped ZnO thin films (Zn1-xLixO, x=0.05-0.15) were grown by pulsed-laser ablation technique. Highly c-axis-oriented films were obtained at a growth temperature of 500 degrees C. Ferroelectricity in Zn1-xLixO was found from the temperature-dependent dielectric constant and from the polarization hysteresis loop. The transition temperature (T-c) varied from 290 to 330 K as the Li concentration increased from 0.05 to 0.15. It was found that the maximum value of the dielectric constant at T-c is a function of Li concentration. A symmetric increase in memory window with the applied gate voltage is observed for the ferroelectric thin films on a p-type Si substrate. A ferroelectric P-E hysteresis loop was observed for all the compositions. The spontaneous polarization (P-s) and coercive field (E-c) of 0.6 mu C/cm(2) and 45 kV/cm were obtained for Zn0.85Li0.15O thin films. These observations reveal that partial replacement of host Zn by Li ions induces a ferroelectric phase in the wurtzite-ZnO semiconductor. The dc transport studies revealed an Ohmic behavior in the lower-voltage region and space-charge-limited conduction prevailed at higher voltages. The optical constants were evaluated from the transmission spectrum and it was found that Li substitution in ZnO enhances the dielectric constant.

Unified large and small signal non-quasi-static model for long channel symmetric DG MOSFET

We propose a unified model for large signal and small signal non-quasi-static analysis of long channel symmetric double gate MOSFET. The model is physics based and relies only on the very basic approximation needed for a charge-based model. It is based on the EKV formalism Enz C, Vittoz EA. Charge based MOS transistor modeling. Wiley; 2006] and is valid in all regions of operation and thus suitable for RF circuit design. Proposed model is verified with professional numerical device simulator and excellent agreement is found. (C) 2010 Elsevier Ltd. All rights reserved.

System effects in double‐channel gated‐integrator‐based deep‐level transient spectroscopy

The effects of the two sampling gate positions, and their widths and the integrator response times on the position, height, and shape of the peaks obtained in a double‐channel gated‐integrator‐based deep‐level transient spectroscopy (DLTS) system are evaluated. The best compromise between the sensitivity and the resolution of the DLTS system is shown to be obtained when the ratio of the two sampling gate positions is about 20. An integrator response time of about 100 ms is shown to be suitable for practical values of emission time constants and heating rates generally used.

Analysis of transients in a canal network

A generalised formulation of the mathematical model developed for the analysis of transients in a canal network, under subcritical flow, with any realistic combination of control structures and their multiple operations, has been presented. The model accounts for a large variety of control structures such as weirs, gates, notches etc. discharging under different conditions, namely submerged and unsubmerged. A numerical scheme to compute and approximate steady state flow condition as the initial condition has also been presented. The model can handle complex situations that may arise from multiple gate operations. This has been demonstrated with a problem wherein the boundary conditions change from a gate discharge equation to an energy equation and back to a gate discharge equation. In such a situation the wave strikes a fixed gate and leads to large and rapid fluctuations in both discharge and depth.

Large low-frequency resistance noise in chemical vapor deposited graphene

We report a detailed investigation of resistance noise in single layer graphene films on Si/SiO2 substrates obtained by chemical vapor deposition (CVD) on copper foils. We find that noise in these systems to be rather large, and when expressed in the form of phenomenological Hooge equation, it corresponds to Hooge parameter as large as 0.1-0.5. We also find the variation in the noise magnitude with the gate voltage (or carrier density) and temperature to be surprisingly weak, which is also unlike the behavior of noise in other forms of graphene, in particular those from exfoliation. (C) 2010 American Institute of Physics. doi:10.1063/1.3493655]

Effects of Parasitics and Interface Traps on Ballistic Nanowire FET in the Ultimate Quantum Capacitance Limit

In this paper, we focus on the performance of a nanowire field-effect transistor in the ultimate quantum capacitance limit (UQCL) (where only one subband is occupied) in the presence of interface traps (D-it), parasitic capacitance (C-L), and source/drain series resistance (R-s,R-d), using a ballistic transport model and compare the performance with its classical capacitance limit (CCL) counterpart. We discuss four different aspects relevant to the present scenario, namely: 1) gate capacitance; 2) drain-current saturation; 3) subthreshold slope; and 4) scaling performance. To gain physical insights into these effects, we also develop a set of semianalytical equations. The key observations are as follows: 1) A strongly energy-quantized nanowire shows nonmonotonic multiple-peak C-V characteristics due to discrete contributions from individual subbands; 2) the ballistic drain current saturates better in the UQCL than in the CCL, both in the presence and absence of D-it and R-s,R-d; 3) the subthreshold slope does not suffer any relative degradation in the UQCL compared to the CCL, even with Dit and R-s,R-d; 4) the UQCL scaling outperforms the CCL in the ideal condition; and 5) the UQCL scaling is more immune to R-s,R-d, but the presence of D-it and C-L significantly degrades the scaling advantages in the UQCL.

A Non Quasi-Static Small Signal Model for Long Channel Symmetric DG MOSFET

We propose a compact model for small signal non quasi static analysis of long channel symmetric double gate MOSFET The model is based on the EKV formalism and is valid in all regions of operation and thus suitable for RF circuit design Proposed model is verified with professional numerical device simulator and excellent agreement is found well beyond the cut-off frequency