A Fast-Locking Phase-Locked Loop Using a Seven-State Phase Frequency Detector

A seven-state phase frequency detector (S.S PFD) is proposed for fast-locking charge pump based phase-locked loops (CPPLLs) in this paper. The locking time of the PLL can be significantly reduced by using the seven-state PFD to inject more current into the loop filter. In this stage, the bandwidth of the PLL is increased or decreased to track the phase difference of the reference signal and the feedback signal. The proposed architecture is realized in a standard 0.35 mu m 2P4M CMOS process with a 3.3V supply voltage. The locking time of the proposed PLL is 1.102 mu s compared with the 2.347 mu s of the PLL based on continuous-time PFD and the 3.298 mu s of the PLL based on the pass-transistor tri-state PFD. There are 53.05% and 66.59% reductions of the locking time. The simulation results and the comparison with other PLLs demonstrate that the proposed seven-state PFD is effective to reduce locking time.

A new frequency offset estimation for OFDM-based systems

A new carrier frequency offset estimation scheme in orthogonal frequency division multiplexing (OFDM) is proposed. The scheme includes coarse frequency offset estimation and fine frequency offset estimation. The coarse frequency offset estimation method we present is a improvement of Zhang's method. The estimation range of the new method is as large as the overall signal-band width. A new fine frequency offset estimation algorithm is also discussed in this paper. The new algorithm has a better performance than the Schmidl's algorithm. The system we use to calculate and simulate is based on the high rate WLAN standard adopted by the IEEE 802.11 stanidardization group. Numerical results are presented to demonstrate the performance of the proposed algorithm.

An adaptive frequency synthesizer architecture reducing reference sidebands

An adaptive phase-locked loop (PLL) frequency synthesizer architecture for reducing reference sidebands at the output of the frequency synthesizer is described. The architecture combines two tuning loops: one is the main loop for locking the PLL frequency synthesizer and operating all the time, the other one is auxiliary loop for reducing reference sidebands and operating only when the main loop is closely locked. A 1.8V 1GHz fully integrated CMOS dual-loop frequency synthesizer is designed in a 0.18um CMOS process. The suppression of the reference sidebands of the proposed frequency synthesizer is 13.8dB more than that of the general frequency synthesizer.

A direct digital frequency synthesizer with single-stage delta-sigma interpolator and current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a 4th-order single-stage pipelined delta-sigma interpolator and a 300MS/s 12-bit current-steering DAC based on Q(2) Random Walk switching scheme. The delta-sigma interpolator is used to reduce the phase truncation error and the ROM size. The measured spurious-free dynamic range (SFDR) is greater than 80 dB for 8-bit phase value and 12-bit sine-amplitude output. The DDFS prototype is fabricated in a 0.35um CMOS technology with core area of 1.11mm(2).

A new frequency offset estimation for OFDM-Based systems

A-new-carrier-frequency offset estimation scheme in orthogonal frequency division multiplexing (OFDM) is proposed. The scheme includes coarse frequency offset estimation and fine frequency offset estimation. The coarse frequency offset estimation method we present is a improvement of Zhang's method. The estimation range of the new method is as large as the overall signal-band width. A new fine frequency offset estimation algorithm is also discussed in this paper. The new algorithm has a better performance than the Schmidt's algorithm. The system we use to calculate and simulate is based on the high rate WLAN standard adopted by the IEEE 802.11 standardization group. Numerical results are presented to demonstrate the performance of the proposed algorithm.

A novel fast lock-in phase-locked loop frequency synthesizer with direct frequency presetting circuit

This paper proposes a novel, fast lock-in, phase-locked loop (PLL) frequency synthesizer. The synthesizer includes a novel mixed-signal voltage-controlled oscillator (VCO) with a direct frequency presetting circuit. The frequency presetting circuit can greatly speed up the lock-in process by accurately the presetting oscillation frequency of the VCO. We fully integrated the synthesizer in standard 0.35 mu m, 3.3 V complementary metal-oxide-semiconductors (CMOS) process. The entire chip area is only 0.4 mm(2). The measured results demonstrate that the synthesizer can speed up the lock-in process significantly and the lock-in time is less than 10 mu s over the entire oscillation frequency range. The measured phase noise of the synthesizer is -85 dBc/Hz at 10 kHz offset. The synthesizer avoids the tradeoff between the lock-in speed and the phase noise/spurs. The synthesizer monitors the chip temperature and automatically compensates for the variation in frequency with temperature.

A direct digital frequency synthesizer with fourth-order phase domain Delta Sigma noise shaper and 12-bit current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage Delta Sigma interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q(2) Random Walk switching scheme. The Delta Sigma interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage Delta Sigma noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35-mu m CMOS technology with active area of 1.11 mm(2) including a 12-bit DAC. The measured DDFS spurious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm(2). The total power consumption of the DDFS is 200)mW with a 3.3-V power supply.

An Accurate and Fast Behavioral Model for PLL Frequency Synthesizer Phase Noise/Spurs Prediction

This paper presents a behavior model for PLL Frequency Synthesizer. All the noise sources are modeled with noise voltages or currents in time-domain. An accurate VCO noise model is introduced, including both thermal noise and 1/f noise. The behavioral model can be co-simulated with transistor level circuits with fast speed and provides more accurate phase noise and spurs prediction. Comparison shows that simulation results match very well with measurement results.

A Novel 0.72-6.2GHz Continuously-Tunable Delta Sigma Fractional-N Frequency Synthesizer

This paper presents a wideband Delta Sigma-based fractional-N synthesizer with three integrated quadrature VCOs for multiple-input multiple-output (MIMO) wireless communication applications. It continuously covers a wide range frequency from 0.72GHz to 6.2GHz that is suitable for multiple communication standards. The synthesizer is designed in 0.13-um RE CMOS process. The dual clock full differential multi-modulus divide (MMD) with low power consumption can operate over 9GHz under the worst condition. In the whole range frequency from 0.72GHz to 6.2GHz, the maximal tuning range of the QVCOs reaches 33.09% and their phase noise is -119d8/Hz similar to 124d8/Hz @1MHz. Its current is less than 12mA at a 1.2V voltage supply when it operates at the highest frequency of 6.2GHz.

A Smart Frequency Presetting Technique for Fast Lock-in LC-PLL Frequency Synthesizer

This paper proposes a smart frequency presetting technique for fast lock-in LC-PLL frequency synthesizer. The technique accurately presets the frequency of VCO with small initial frequency error and greatly reduces the lock-in time. It can automatically compensate preset frequency variation with process and temperature. A 2.4GHz synthesizer with 1MHz reference input was implemented in 0.35 mu m CMOS process. The chip core area is 0.4mm(2). Output frequency of VCO ranges from 2390 to 2600MHz. The measured results show that the typical lock-in time is 3 mu s. The phase noise is -112dBc/Hz at 600KHz offset from center frequency. The test chip consumes current of 22mA that includes the consumption of the I/O buffers.

12 W high efficiency single frequency ring laser

Single-frequency output power of 12 W at 1064 nm is demonstrated. Pumped by a fiber-coupled diode laser, the Nd:YVO4 produces 58.6% of the slope efficiency with respect to absorbed pump power, and 52.7% of the optical-optical efficiency and nearly diffraction-limited output with a beam quality parameter of M-2 approximate to 1.11. To the best of our knowledge, this is the highest slope efficiency and optical-optical efficiency in single-frequency Nd:YVO4 ring laser. The slope efficiency of the single frequency laser is close to the limit of the efficiency. [GRAPHICS] output spectrum of the single-frequency Nd:YVO4 ring laser

Ultrafast sum-frequency polarization beats in twin Markovian stochastic correlation

An analytic closed form for the second- order or fourth- order Markovian stochastic correlation of attosecond sum- frequency polarization beat ( ASPB) can be obtained in the extremely Doppler- broadened limit. The homodyne detected ASPB signal is shown to be particularly sensitive to the statistical properties of the Markovian stochastic light. fields with arbitrary bandwidth. The physical explanation for this is that the Gaussian- amplitude. field undergoes stronger intensity. fluctuations than a chaotic. field. On the other hand, the intensity ( amplitude). fluctuations of the Gaussian- amplitude. field or the chaotic. field are always much larger than the pure phase. fluctuations of the phase-diffusion field. The field correlation has weakly influence on the ASPB signal when the laser has narrow bandwidth. In contrast, when the laser has broadband linewidth, the ASPB signal shows resonant- nonresonant cross correlation, and the sensitivities of ASPB signal to three Markovian stochastic models increase as time delay is increased. A Doppler- free precision in the measurement of the energy- level sum can be achieved with an arbitrary bandwidth. The advantage of ASPB is that the ultrafast modulation period 900as can still be improved, because the energy- level interval between ground state and excited state can be widely separated.

Coherent laser control in attosecond sum-frequency polarization beats using twin noisy driving fields

Based on the phase-conjugate polarization interference between two-pathway excitations, we obtained an analytic closed form for the second-order or fourth-order Markovian stochastic correlation of the V three-level sum-frequency polarization beat (SFPB) in attosecond scale. Novel interferometric oscillatory behavior is exposed in terms of radiation-radiation, radiation-matter, and matter-matter polarization beats. The phase-coherent control of the light beams in the SFPB is subtle. When the laser has broadband linewidth, the homodyne detected SFPB signal shows resonant-nonresonant cross correlation, a drastic difference for three Markovian stochastic fields, and the autocorrelation of the SFPB exhibits hybrid radiation-matter detuning terahertz damping oscillation. As an attosecond ultrafast modulation process, it can be extended intrinsically to any sum frequency of energy levels. It has been also found that the asymmetric behaviors of the polarization beat signals due to the unbalanced controllable dispersion effects between the two arms of interferometer do not affect the overall accuracy in case using the SFPB to measure the Doppler-free energy-level sum of two excited states.

Phase and amplitude reconstruction from a single carrier-frequency interferogram without phase unwrapping

A rapid algorithm for phase and amplitude reconstruction from a single spatial-carrier interferogram is proposed by bringing a phase-shifting mechanism into reconstruction of a carrier-frequency interferogram. The algorithm reconstructs phase through directly obtaining and integrating its real-value derivatives, avoiding a phase unwrapping process. The proposed method is rapid and easy to implement and is made insensitive to the profile of the interferogram boundaries by choosing a suitable integrating path. Moreover, the algorithm can also be used to reconstruct the amplitude of the object wave expediently without retrieving the phase profile in advance. The feasibility of this algorithm is demonstrated by both numerical simulation and experiment. (c) 2008 Optical Society of America.