CMOS集成电路用Φ150-200mm外延硅材料

报道了Φ150mm CMOS硅外延材料的研究开发及集成电路应用成果，对Φ200mmP/P~-硅外延材料进行了初步探索研究。Φ150mm P/P~+硅外延片实现了批量生产，并成功应用于集成电路生产线，芯片成品率大于80%。硅外延片的参数指标能满足集成电路制造要求。

部分耗尽CMOS/SOI工艺

对部分耗尽CMOS/SOI工艺进行了研究，成功地开发出成套部分耗尽CMOS/SOI抗辐照工艺。其关键工艺技术包括

CMOS/SOI64Kb静态随机存储器

于2010-11-23批量导入

高精度单向模拟开关的设计及其基于CMOS工艺的电路实现

提出并设计了一种基于CMOS工艺实现的高速高精度的单向隔离模拟开关，该开关用在高速两步法A/D转换器中使电路结构大为简化。通过对开关特性的理论分析与电路模拟，证明了这种模拟开关具有高速可控性，传输信号的精度优于先前研究的双极单向隔离模拟开关。

Optoelectronic Smart Pixels Comprising Flip-Chip-Bonded GaAs/AlGaAs MQW Detectors and Modulators on Silicon CMOS Circuit

于2010-11-23批量导入

用于先进 CMOS电路的 150 mm硅外延片外延生长(英文)

随着大规模和超大规模集成电路特征尺寸向亚微米、深亚微米发展，下一代集成电路对硅片的表面晶体完整性和电学性能提出了更高的要求。与含有高密度晶体原生缺陷的硅抛光片相比，硅外延片一般能满足这些要求。该文报道了应用于先进集成电路的150mmP/P~+ CMOS硅外延片研究进展。在PE2061硅外延炉上进行了P/P~+硅外延生长。外延片特征参数，如外延层厚度、电阻率均匀性，过渡区宽度及少子产生寿命进行了详细表征。研究表明:150mm P/P~+CMOS硅外延片能够满足先进集成电路对材料更高要求。

利用改进的固相外延技术改善CMOS/SOS器件的特性

CMOS/SOS器件同体硅CMOS器件相比，载流子迁移率较低，沟道漏电电流放大，它们主要是由异质外延硅膜缺陷，特别是靠近硅蓝宝石界面的硅膜缺陷造成的。该文描述一种改进的固相外延技术提高外延硅膜质量进而改善CMOS/SOS器件特性的实验结果。

硅基光电探测器前置放大电路的输入级CMOS实现

介绍前置电路对光电探测器的影响和给出一种适用于硅基光电探测器前置放大电路的输入级CMOS实现的方法。

16-channel 0.35 mu m CMOS/VCSEL optoelectronic devices

We report some investigations on vertical cavity surface emitting laser (VCSEL) arrays and VCSEL based optoelectronic smart photonic multiple chip modules (MCM), consisting of 1 x 16 vertical cavity surface emitting laser array and 16-channel lasers driver 0.35 mum CMOS circuit. The hybrid integrated multiple chip modules based on VCSEL operate at more than 2GHz in -3dB frequency bandwidth.

Hybrid CMOS/VCSEL optoelectronic modules

We report some investigations on vertical cavity surface emitting laser (VCSEL) arrays and VCSEL based optoelectronic smart photonic multiple chip modules (MCM), consisting of 1x16 vertical cavity surface emitting laser array and 16-channel lasers driver 0.35 Pin CMOS circuit. The hybrid integrated multiple chip modules based on VCSEL operate at more than 2GHz in -3dB frequency bandwidth.

Improvement of CMOS SOS devices characteristics by a modified solid phase epitaxy

CMOS/SOS devices have lower carriers mobility and higher channel leakage current than bulk silicon CMOS devices. These mainly results from the defects of heteroepitaxial silicon film, especially from the defects near Si-Sapphire interface. This paper describes the experiment results of CMOS/SOS devices characteristics improved by a better epitaxial silicon quality which is obtained by a modified solid phase epitaxy.

Flip-chip bonded hybrid CMOS/SEED optoelectronic smart pixels

Hybrid integration of GaAs/AlGaAs multiple quantum well self electro-optic effect device (SEED) arrays are demonstrated flip-chip bonded directly onto 1 mu m silicon CMOS circuits. The GaAs/AlGaAs MQW devices are designed for 850 nm operation. Some devices are used as input light detectors and others serve as output light modulators. The measurement results under applied biases show good optoelectronic characteristics of elements in SEED arrays. Nearly the same reflection spectrum is obtained for the different devices at an array and the contrast ratio is more than 1.2:1 after flip-chip bonding and packaging. The transimpedance receiver-transmitter circuit can be operated at a frequency of 300 MHz.

Behavior of Pentacene Initial Nucleation on Various Dielectrics and Its Effect on Carrier Transport in Organic Field-Effect Transistor

The influence of dielectric surface energy on the initial nucleation and the growth of pentacene films as well as the electrical properties of the pentacene-based field-effect transistors are investigated. We have examined a range of organic and inorganic dielectrics with different surface energies, such as polycarbonate/SiO2, polystyrene/SiO2, and PMMA/SiO2 bi-layered dielectrics and also the bare SiO2 dielectric. Atomic force microscopy measurements of sub-monolayer and thick pentacene films indicated that the growth of pentacene film was in Stranski-Kranstanow growth mode on all the dielectrics. However, the initial nucleation density and the size of the first-layered pentacene islands deposited on different dielectrics are drastically influenced by the dielectric surface energy. With the increasing of the surface energy, the nucleation density increased and thus the average size of pentacene islands for the first mono-layer deposition decreased. The performance of fabricated pentacene-based thin film transistors was found to be highly related to nucleation density and the island size of deposited Pentacene film, and it had no relationship to the final particle size of the thick pentacene film. The field effect mobility of the thin film transistor could be achieved as high as 1.38 cm(2)/Vs with on/off ratio over 3 x 10(7) on the PS/SiO2 where the lowest surface energy existed among all the dielectrics. For comparison, the values of mobility and on/off ratio were 0.42 cm(2)/Vs and 1 x 10(6) for thin film transistor deposited directly on bare SiO2 having the highest surface energy.