Normal incidence p-i-n Ge heterojunction photodiodes on Si substrate grown by ultrahigh vacuum chemical vapor deposition

We report on normal incidence p-i-n heterojunction photodiodes operating in the near-infrared region and realized in pure germanium on planar silicon substrate. The diodes were fabricated by ultrahigh vacuum chemical vapor deposition at 600 degrees C without thermal annealing and allowing the integration with standard silicon processes. Due to the 0.14% residual tensile strain generated by the thermal expansion mismatch between Ge and Si, an efficiency enhancement of nearly 3-fold at 1.55 mu m and the absorption edge shifting to longer wavelength of about 40 nm are achieved in the epitaxial Ge films. The diode with a responsivity of 0.23 A/W at 1.55 mu m wavelength and a bulk dark current density of 10 mA/cm(2) is demonstrated. These diodes with high performances and full compatibility with the CMOS processes enable monolithically integrating microphotonics and microelectronics on the same chip.

Sub-nanosecond silicon-on-insulator optical micro-ring switch with low crosstalk

We demonstrate a sub-nanosecond electro-optical switch with low crosstalk in a silicon-on-insulator (SOI) dual-coupled micro-ring embedded with p-i-n diodes. A crosstalk of -23 dB is obtained in the 20-mu m-radius micro-ring with the well-designing asymmetric dual-coupling structure. By optimizations of the doping profiles and the fabrication processes, the sub-nanosecond switch-on/off time of < 400 ps is finally realized under an electrical pre-emphasized driving signal. This compact and fast-response micro-ring switch, which can be fabricated by complementary metal oxide semiconductor (CMOS) compatible technologies, have enormous potential in optical interconnects of multicore networks-on-chip.

Wafer-Level Testable High-Speed Silicon Microring Modulator Integrated with Grating Couplers

A wafer-level testable silicon-on-insulator-based microring modulator is demonstrated with high modulation speed, to which the grating couplers are integrated as the fiber-to-chip interfaces. Cost-efficient fabrications are realized with the help of optical structure and etching depth designs. Grating couplers and waveguides are patterned and etched together with the same slab thickness. Finally we obtain a 3-dB coupling bandwidth of about 60nm and 10 Gb/s nonreturn-to-zero modulation by wafer-level optical and electrical measurements.

硅基级联谐振腔结构的低功耗电光调制器

本发明公开了一种硅基级联谐振腔结构的低功耗电光调制器，该电光调制器由制作在绝缘体上硅SOI衬底上的两个法布里-珀罗谐振腔(4)串联而成，该两个法布里-珀罗谐振腔(4)采用游标式级联的形式串联形成级联谐振腔结构的低功耗电光调制器。所述法布里-珀罗谐振腔(4)由两个布拉格光栅(3)与位于该两个布拉格光栅之间的脊形波导(1)构成，布拉格光栅(3)作为该法布里-珀罗谐振腔(4)的反射镜。本发明大幅提高了谐振腔的F值、FSR、Q值等参数，使得电光调制器的消光比大大增加，调制所需功耗更小，速度更快，而且器件结构紧凑，制作工艺与成熟的微电子CMOS工艺兼容。

Development of high-k gate dielectric materials

The traditional gate dielectric material Of SiO2 can not satisfy the need of the continuous downscaling of CMOS dimensions. High-K gate dielectric materials have attracted extensive research efforts recently and obtained great progress. In this paper, the developments of high-K gate materials were reviewed. Based on the author's background and research work in the area, the latest achievements of high-K gate dielectric materials on the recrystalization temperature, the low-K interface layer, and the dielectric breakdown and metal gate electrode were introduced in detail.

Compact voltage-mode multi-valued literal gate using nanoscale ballistic MOSFETs

A CMOS voltage-mode multi-valued literal gate is presented. The ballistic electron transport characteristic of nanoscale MOSFETs is smartly used to compactly achieve universal radix-4 literal operations. The proposed literal gates have small numbers of transistors and low power dissipations, which makes them promising for future nanoscale multi-valued circuits. The gates are simulated by HSPICE.

Fabrication and characterization of active and sequential circuits utilizing Schottky-wrap-gate-controlled GaAs hexagonal nanowire network structures

For realization of hexagonal BDD-based digital systems, active and sequential circuits including inverters, flip flops and ring oscillators are designed and fabricated on GaAs-based hexagonal nanowire networks controlled by Schottky wrap gates (WPGs), and their operations are characterized. Fabricated inverters show comparatively high transfer gain of more than 10. Clear and correct operation of hexagonal set-reset flip flops (SR-FFs) is obtained at room temperature. Fabricated hexagonal D-type flip flop (D-FF) circuits integrating twelve WPG field effect transistors (FETs) show capturing input signal by triggering although the output swing is small. Oscillatory output is successfully obtained in a fabricated 7-stage hexagonal ring oscillator. Obtained results confirm that a good possibility to realize practical digital systems can be implemented by the present circuit approach.

A programmable SIMD vision chip for real-time vision applications

A programmable vision chip for real-time vision applications is presented. The chip architecture is a combination of a SIMD processing element array and row-parallel processors, which can perform pixel-parallel and row-parallel operations at high speed. It implements the mathematical morphology method to carry out low-level and mid-level image processing and sends out image features for high-level image processing without I/O bottleneck. The chip can perform many algorithms through software control. The simulated maximum frequency of the vision chip is 300 MHz with 16 x 16 pixels resolution. It achieves the rate of 1000 frames per second in real-time vision. A prototype chip with a 16 x 16 PE array is fabricated by the 0.18 mu m standard CMOS process. It has a pixel size of 30 mu m x 40 mu m and 8.72 mW power consumption with a 1.8 V power supply. Experiments including the mathematical morphology method and target tracking application demonstrated that the chip is fully functional and can be applied in real-time vision applications.

Development of solar-blind AlGaN 128x128 ultraviolet focal plane arrays

This paper reports the development of solar-blind aluminum gallium nitride (AlGaN) 128x128 UV Focal Plane Arrays (FPAs). The back-illuminated hybrid FPA architecture consists of an 128x128 back-illuminated AlGaN PIN detector array that is bump-mounted to a matching 128x128 silicon CMOS readout integrated circuit (ROIC) chip. The 128x128 p-i-n photodiode arrays with cuton and cutoff wavelengths of 233 and 258 nm, with a sharp reduction in response to UVB (280-320 nm) light. Several examples of solar-blind images are provided. This solar-blind band FPA has much better application prospect.

Compact non-binary fast adders using single-electron devices

This paper proposes compact adders that are based on non-binary redundant number systems and single-electron (SE) devices. The adders use the number of single electrons to represent discrete multiple-valued logic state and manipulate single electrons to perform arithmetic operations. These adders have fast speed and are referred as fast adders. We develop a family of SE transfer circuits based on MOSFET-based SE turnstile. The fast adder circuit can be easily designed by directly mapping the graphical counter tree diagram (CTD) representation of the addition algorithm to SE devices and circuits. We propose two design approaches to implement fast adders using SE transfer circuits the threshold approach and the periodic approach. The periodic approach uses the voltage-controlled single-electron transfer characteristics to efficiently achieve periodic arithmetic functions. We use HSPICE simulator to verify fast adders operations. The speeds of the proposed adders are fast. The numbers of transistors of the adders are much smaller than conventional approaches. The power dissipations are much lower than CMOS and multiple-valued current-mode fast adders. (C) 2009 Elsevier Ltd. All rights reserved.

A Fully Integrated 900-MHz Passive RFID Transponder Front End With Novel Zero-Threshold RF-DC Rectifier

This paper presents a fully integrated CMOS analog front end for a passive 900-MHz radio-frequency identification (RFID) transponder. The power supply in this front end is generated from the received RF electromagnetic energy by using an RF-dc voltage rectifier. In order to improve the compatibility with standard CMOS technology, Schottky diodes in conventional RF-dc rectifiers are replaced by diode-connected MOS transistors with zero threshold. Meanwhile, theoretical analyses for the proposed rectifier are provided and verified by both simulation and measurement results. The design considerations of the pulsewidth-modulation (PWM) demodulator and the backscatter modulator in the front end are also discussed for low-power applications. The proposed front end is implemented in a 0.35-mu m 2P4M CMOS technology. The whole chip occupies a die area of 490 x 780 mu m(2) and consumes only 2.1 mu W in reading mode under a self-generated 1.5-V supply voltage. The measurement results show that the proposed rectifier can properly operate with a - 14.7-dBm input RF power at a power conversion efficiency of 13.0%. In the proposed RFID applications, this sensitivity corresponds to 10.88-m communication distance at 4-W equivalent isotropically radiated power from a reader base station.

A 1,000 Frames/s Programmable Vision Chip with Variable Resolution and Row-Pixel-Mixed Parallel Image Processors

A programmable vision chip with variable resolution and row-pixel-mixed parallel image processors is presented. The chip consists of a CMOS sensor array, with row-parallel 6-bit Algorithmic ADCs, row-parallel gray-scale image processors, pixel-parallel SIMD Processing Element (PE) array, and instruction controller. The resolution of the image in the chip is variable: high resolution for a focused area and low resolution for general view. It implements gray-scale and binary mathematical morphology algorithms in series to carry out low-level and mid-level image processing and sends out features of the image for various applications. It can perform image processing at over 1,000 frames/s (fps). A prototype chip with 64 x 64 pixels resolution and 6-bit gray-scale image is fabricated in 0.18 mu m Standard CMOS process. The area size of chip is 1.5 mm x 3.5 mm. Each pixel size is 9.5 mu m x 9.5 mu m and each processing element size is 23 mu m x 29 mu m. The experiment results demonstrate that the chip can perform low-level and mid-level image processing and it can be applied in the real-time vision applications, such as high speed target tracking.

A novel vision chip for high-speed target tracking

This paper presents a novel vision chip for high-speed target tracking. Two concise algorithms for high-speed target tracking are developed. The algorithms include some basic operations that can be used to process the real-time image information during target tracking. The vision chip is implemented that is based on the algorithms and a row-parallel architecture. A prototype chip has 64 x 64 pixels is fabricated by 0.35 pm complementary metal-oxide-semiconductor transistor (CMOS) process with 4.5 x 2.5 mm(2) area. It operates at a rate of 1000 frames per second with 10 MHz chip main clock. The experiment results demonstrate that a high-speed target can be tracked in complex static background and a high-speed target among other high-speed objects can be tracked in clean background.

A bistable, self-latching inverter by the monolithic integration of resonant tunnelling diode and high electron mobility transistor

This paper reports that the structures of AlGaAs/InGaAs high electron mobility transistor (HEMT) and AlAs/GaAs resonant tunnelling diode (RTD) are epitaxially grown by molecular beam epitaxy ( MBE) in turn on a GaAs substrate. An Al0.24Ga0.76As chair barrier layer, which is grown adjacent to the top AlAs barrier, helps to reduce the valley current of RTD. The peak-to-valley current ratio of fabricated RTD is 4.8 and the transconductance for the 1-mu m gate HEMT is 125mS/mm. A static inverter which consists of two RTDs and a HEMT is designed and fabricated. Unlike a conventional CMOS inverter, the novel inverter exhibits self-latching property.

Metal catalysis-free, direction-controlled planar growth of single-crystalline alpha-Si3N4 nanowires on Si(100) substrate

Single-crystalline alpha-Si3N4 nanowires are controlled to grow perpendicular to the wet-etched trenches in the SiO0.94 film on the plane of the Si substrate without metal catalysis. A detailed characterization is carried out by scanning electron microscopy (SEM) and transmission electron microscopy (TEM). The photoluminescence at 600 nm from alpha-Si3N4 nanowires is attributed to the recombination at the defect state formed by the Si dangling bond N3 equivalent to Si-center dot. The growth mechanism is considered to be related to the catalysis and nitridation of SiO nanoclusters preferably re-deposited around the inner corner of the trenches, as well as faster Si diffusion along the slanting side walls of the trenches. This simple direction-controlled growth method is compatible with the CMOS process, and could facilitate the fabrication of alpha-Si3N4 nanoelectronic or nanophotonic devices on the Si platform.