Zn~(2+)浓度对固氮鱼腥藻(Anabaena azotica Ley)光能转化特性的影响

本实验对在不同Zn2+浓度条件下培养的固氮鱼腥藻(Anabaena azoticaLey)的生长、光合放氧速率和叶绿素荧光参数Fv/Fm进行了测定.结果表明,当Zn2+浓度为1.0μmol/L时,其比生长速率(Specific growth rate)最大,光合放氧速率和Fv/Fm值最高.当Zn2+浓度大于等于5.0μmol/L时会抑制A.azotica Ley的生长和光合作用.对在0μmol/L和5.0μmol/L Zn2+浓度下生长的藻细胞藻胆体-类囊体膜复合物吸收光谱的比较和对与5.0μmol/L

A low-cost CMOS programmable temperature

A novel uncalibrated CMOS programmable temperature switch with high temperature accuracy is presented. Its threshold temperature T-th can be programmed by adjusting the ratios of width and length of the transistors. The operating principles of the temperature switch circuit is theoretically explained. A floating gate neural MOS circuit is designed to compensate automatically the threshold temperature T-th variation that results form the process tolerance. The switch circuit is implemented in a standard 0.35 mu m CMOS process. The temperature switch can be programmed to perform the switch operation at 16 different threshold temperature T(th)s from 45-120 degrees C with a 5 degrees C increment. The measurement shows a good consistency in the threshold temperatures. The chip core area is 0.04 mm(2) and power consumption is 3.1 mu A at 3.3V power supply. The advantages of the temperature switch are low power consumption, the programmable threshold temperature and the controllable hysteresis.

A Fully Integrated 900-MHz Passive RFID Transponder Front End With Novel Zero-Threshold RF-DC Rectifier

This paper presents a fully integrated CMOS analog front end for a passive 900-MHz radio-frequency identification (RFID) transponder. The power supply in this front end is generated from the received RF electromagnetic energy by using an RF-dc voltage rectifier. In order to improve the compatibility with standard CMOS technology, Schottky diodes in conventional RF-dc rectifiers are replaced by diode-connected MOS transistors with zero threshold. Meanwhile, theoretical analyses for the proposed rectifier are provided and verified by both simulation and measurement results. The design considerations of the pulsewidth-modulation (PWM) demodulator and the backscatter modulator in the front end are also discussed for low-power applications. The proposed front end is implemented in a 0.35-mu m 2P4M CMOS technology. The whole chip occupies a die area of 490 x 780 mu m(2) and consumes only 2.1 mu W in reading mode under a self-generated 1.5-V supply voltage. The measurement results show that the proposed rectifier can properly operate with a - 14.7-dBm input RF power at a power conversion efficiency of 13.0%. In the proposed RFID applications, this sensitivity corresponds to 10.88-m communication distance at 4-W equivalent isotropically radiated power from a reader base station.

1 x 4 Ge-on-SOI PIN Photodetector Array for Parallel Optical Interconnects

High-quality Ge film was epitaxially grown on silicon on insulator using the ultrahigh vacuum chemical vapor deposition. In this paper, we demonstrated that the efficient 1 4 germanium-on-silicon p-i-n photodetector arrays with 1.0 mu m Ge film had a responsivity as high as 0.65 A/W at 1.31 mu m and 0.32 A/W at 1.55 mu m, respectively. The dark current density was about 0.75 mA/cm(2) at 0 V and 13.9 mA/cm(2) at 1.0 V reverse bias. The detectors with a diameter of 25 mu m were measured at 1550 nm incident light under 0 V bias, and the result showed that the 3-dB bandwidth is 2.48 GHz. At a reverse bias of 3 V, the bandwidth is about 13.3 GHz. The four devices showed a good consistency.

Effect of In0.2Ga0.8As and In0.2Al0.8As combination layer on band offsets of InAs quantum dots

We demonstrate the self-organized InAs quantum dots capped with thin and In0.2Al0.8As and In0.2Ga0.8As combination layers with a large ground and first excited energy separation emission at 1.35 mum at room temperature. Deep level transient spectroscopy is used to obtain quantitative information on emission activation energies and capture barriers for electrons and holes. For this system, the emission activation energies are larger than those for InAs/GaAs quantum dots. With the properties of wide energy separation and deep emission activation energies, self-organized InAs quantum dots capped with In0.2Al0.8As and In0.2Ga0.8As combination layers are one of the promising epitaxial structures of 1.3 mum quantum dot devices. (C) 2004 American Institute of Physics.

Silicon light emitting devices in CMOS technology

Two silicon light emitting devices with different structures are realized in standard 0.35 mu m complementary metal-oxide-semiconductor (CMOS) technology. They operate in reverse breakdown mode and can be turned on at 8.3 V. Output optical powers of 13.6 nW and 12.1 nW are measured at 10 V and 100 mA, respectively, and both the calculated light emission intensities are more than 1 mW/Cm-2. The optical spectra of the two devices are between 600-790 nm with a clear peak near 760 nm..

MBE InAs quantum dots grown on metamorphic InGaAs for long wavelength emitting

GaAs-based InAs quantum dots using InGaAs composition-graded metamorphic layers have been investigated by molecular beam epitaxy. Emission with the wavelength similar to 1.5 mu m from the dots was obtained at room temperature with the relatively large full width at half maximum. The emission wavelength is relatively stable when subjected to fast annealing. The number density of dots reached similar to 6 x 10(10) cm(-2). Undulated morphology was observed on the surface of the sample, which has some influence on the dot size and distribution. In epilayers, misfit dislocations were confined within the step-graded InGaAs metamorphic buffer layer. (c) 2006 Elsevier B.V. All rights reserved.

A novel fast lock-in phase-locked loop frequency synthesizer with direct frequency presetting circuit

This paper proposes a novel, fast lock-in, phase-locked loop (PLL) frequency synthesizer. The synthesizer includes a novel mixed-signal voltage-controlled oscillator (VCO) with a direct frequency presetting circuit. The frequency presetting circuit can greatly speed up the lock-in process by accurately the presetting oscillation frequency of the VCO. We fully integrated the synthesizer in standard 0.35 mu m, 3.3 V complementary metal-oxide-semiconductors (CMOS) process. The entire chip area is only 0.4 mm(2). The measured results demonstrate that the synthesizer can speed up the lock-in process significantly and the lock-in time is less than 10 mu s over the entire oscillation frequency range. The measured phase noise of the synthesizer is -85 dBc/Hz at 10 kHz offset. The synthesizer avoids the tradeoff between the lock-in speed and the phase noise/spurs. The synthesizer monitors the chip temperature and automatically compensates for the variation in frequency with temperature.

A direct digital frequency synthesizer with fourth-order phase domain Delta Sigma noise shaper and 12-bit current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage Delta Sigma interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q(2) Random Walk switching scheme. The Delta Sigma interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage Delta Sigma noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35-mu m CMOS technology with active area of 1.11 mm(2) including a 12-bit DAC. The measured DDFS spurious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm(2). The total power consumption of the DDFS is 200)mW with a 3.3-V power supply.

Effect of InAlAs/InGaAs cap layer on optical properties of self-assembled InAs/GaAs quantum dots

We have investigated the effect of InAlAs/InGaAs cap layer on the optical properties of self-assembled InAs/GaAs quantum dots (QDs). We find that the photoluminescence emission energy, linewidth and the energy separation between the ground and first excited states of InAs QDs depend on the In composition and the thickness of thin InAlAs cap layer. Furthermore, the large energy separation of 103 meV was obtained from InAs/GaAs QDs with emission at 1.35 pm at room temperature. (C) 2002 Elsevier Science B.V. All rights reserved.

Photoluminescence study of self-assembled InAs/GaAs quantum dots covered by an InAlAs and InGaAs combination layer

We have fabricated a quantum dot (QD) structure for long-wavelength temperature-insensitive semiconductor laser by introducing a combined InAlAs and InGaAs overgrowth layer on InAs/GaAs QDs. We found that QDs formed on GaAs (100) substrate by InAs deposition followed by the InAlAs and InGaAs combination layer demonstrate two effects: one is the photoluminescence peak redshift towards 1.35 mum at room temperature, the other is that the energy separation between the ground and first excited states can be up to 103 meV. These results are attributed to the fact that InAs/GaAs intermixing caused by In segregation at substrate temperature of 520 degreesC can be considerably suppressed by the thin InAlAs layer and the strain in the quantum dots can be reduced by the combined InAlAs and InGaAs layer. (C) 2002 American Institute of Physics.

Pockels effect in GaN/Al-x,Gal(1-x)N superlattice with different quantum structures - art. no. 69841G

The linear electro-optic (Pockels) effect of wurtzite gallium nitride (GaN) films and six-period GaN/AlxGa1-xN superlattices with different quantum structures were demonstrated by a polarization-maintaining fiber-optical Mach-Zehnder interferometer system with an incident light wavelength of 1.55 mu m. The samples were prepared on (0001) sapphire substrate by low-temperature metalorganic chemical vapor deposition (MOCVD). The measured coefficients of the GaN/AlxGa1-xN superlattices are much larger than those of bulk material. Taking advantage of the strong field localization due to resonances, GaN/AlxGa1-xN SL can be proposed to engineer the nonlinear responses.

A direct-conversion mixer with a DC-offset cancellation for WLAN

This paper presents a 5GHz double-balanced mixer with DC-offset cancellation circuit for direct-conversion receiver compliant with IEEE 802.11a wireless LAN standard. The analog feedback loop is used, to eliminate the DC-offset at the output of the double-balanced mixer. The test results show that the mixer with DC-offset cancellation circuit has voltage conversion gain of 9.5dB at 5.15GHz, noise figure of 13.5dB, IIP3 of 7.6 dBm, 1.73mV DC-offset voltage and 67mW power with 3.3-V power supply. The DC-offset cancellation circuit has less than 0.1mm(2) additional area and 0.3mW added power dissipation. The direct conversion WLAN receiver has been implemented in a 0.35 mu m SiGe BiCMOS technology.

Monolithic Integration of Light Emitting Diodes, Photodetector and Receiver Circuit in Standard CMOS Technology

A monolithic silicon CMOS optoelectronic integrated circuit (OEIC) is designed and fabricated with standard 0.35 mu m CMOS technology. This OEIC circuit consists of light emitting diodes (LED), silicon dioxide waveguide, photodiodes and receiver circuit. The silicon LED operates in reverse breakdown mode and can be turned on at 8.5V 10mA. The silicon dioxide waveguide is composed of multiple layers of silicon dioxide between different metals layers. A two PN-junctions photodetector composed of n-well/p-substrate junction and p(+) active implantation/n-well junction maximizes the depletion region width. The readout circuitry in pixels is exploited to handle as small as 0.1nA photocurrent. Simulation and testing results show that the optical emissions powers are about two orders higher than the low frequency detectivity of silicon CMOS photodetcctor and receiver circuit.

A Fast-Locking Phase-Locked Loop Using a Seven-State Phase Frequency Detector

A seven-state phase frequency detector (S.S PFD) is proposed for fast-locking charge pump based phase-locked loops (CPPLLs) in this paper. The locking time of the PLL can be significantly reduced by using the seven-state PFD to inject more current into the loop filter. In this stage, the bandwidth of the PLL is increased or decreased to track the phase difference of the reference signal and the feedback signal. The proposed architecture is realized in a standard 0.35 mu m 2P4M CMOS process with a 3.3V supply voltage. The locking time of the proposed PLL is 1.102 mu s compared with the 2.347 mu s of the PLL based on continuous-time PFD and the 3.298 mu s of the PLL based on the pass-transistor tri-state PFD. There are 53.05% and 66.59% reductions of the locking time. The simulation results and the comparison with other PLLs demonstrate that the proposed seven-state PFD is effective to reduce locking time.