109 resultados para progetto PCB nodo sensore wireless ultra low power monitoraggio della temperatura


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Si-based optoelectronic devices, including stimulated emission from Si diode, 1.3 and 1.5mum SiGe photodetector with quantum structures, 1GHz MOS optical modulator, SOI optical switch matrix and wavelength tunable filter are reviewed in the paper.

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We demonstrate 10 Gb/s directly-modulated 1.3 mu m InAs quantum-dot (QD) lasers grown on GaAs substrates by molecular beam epitaxy. The active region of the QD lasers consists of five-stacked InAs QD layers. Ridge-waveguide lasers with a ridge width of 4 mu m and a cavity length of 600 mu m are fabricated with standard lithography and wet etching techniques. It is found that the lasers emit at 1293 nm with a very low threshold current of 5 mA at room temperature. Furthermore, clear eye-opening patterns under 10 Gb/s modulation rate at temperatures of up to 50 degrees C are achieved by the QD lasers. The results presented here have important implications for realizing low-cost, low-power-consumption, and high-speed light sources for next-generation communication systems.

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The influences of channel layer width, spacer layer width, and delta-doping density on the electron density and its distribution in the AlSb/InAs high electron mobility transistors (HEMTs) have been studied based on the self-consistent calculation of the Schrodinger and Poisson equations with both the strain and nonparabolicity effects being taken into account. The results show that, having little influence on the total two dimensional electron gas (2DEG) concentration in the channel, the HEMT's channel layer width has some influence on the electron mobility, with a channel as narrow as 100-130 angstrom being more beneficial. For the AlSb/InAs HEMT with a Te delta-doped layer, the 2DEG concentration as high as 9.1 X 10(12) cm(-2) can be achieved in the channel by enhancing the delta-doping concentration without the occurrence of the parallel conduction. When utilizing a Si delta-doped InAs layer as the electron-supplying layer of the AlSb/InAs HEMT, the effect of the InAs donor layer thickness is studied on the 2DEG concentration. To obtain a higher 2DEG concentration in the channel, it is necessary to use an InAs donor layer as thin as 4 monolayer. To test the validity of our calculation, we have compared our theoretical results (2DEG concentration and its distribution in different sub-bands of the channel) with the experimental ones done by other groups and show that our theoretical calculation is consistent with the experimental results.

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In this paper we report on the first results of epitaxial growth of GaN layers on GaAs (100) substrates using a modified MBE system, equipped with a DC-plasma source for nitrogen activation in configuration of reverse magnetron at ultra-low pressures.

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This paper proposes a novel noise optimization technique. The technique gives analytical formulae for the noise performance of inductively degenerated CMOS low noise amplifier (LNA) circuits with an ideal gate inductor for a fixed bias voltage and nonideal gate inductor for a fixed power dissipation, respectively, by mathematical analysis and reasonable approximation methods. LNA circuits with required noise figure can be designed effectively and rapidly just by using hand calculations of the proposed formulae. We design a 1.8 GHz LNA in a TSMC 0.25 pan CMOS process. The measured results show a noise figure of 1.6 dB with a forward gain of 14.4 dB at a power consumption of 5 mW, demonstrating that the designed LNA circuits can achieve low noise figure levels at low power dissipation.

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A low-power, highly linear, multi-standard, active-RC filter with an accurate and novel tuning architec-ture is presented. It exhibits 1EEE 802. 11a/b/g (9.5 MHz) and DVB-H (3 MHz, 4 MHz) application. The filter exploits digitally-controlled polysilicon resistor banks and a phase lock loop type automatic tuning system. The novel and complex automatic frequency calibration scheme provides better than 4 comer frequency accuracy, and it can be powered down after calibration to save power and avoid digital signal interference. The filter achieves OIP3 of 26 dBm and the measured group delay variation of the receiver filter is 50 ns (WLAN mode). Its dissipation is 3.4 mA in RX mode and 2.3 mA (only for one path) in TX mode from a 2.85 V supply. The dissipation of calibration consumes 2 mA. The circuit has been fabricated in a 0.35μm 47 GHz SiGe BiCMOS technology; the receiver and transmitter filter occupy 0.21 mm~2 and 0.11 mm~2 (calibration circuit excluded), respectively.

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A compact direct digital frequency synthesizer (DDFS) for system-on-chip implementation of the high precision rubidium atomic frequency standard is developed. For small chip size and low power consumption, the phase to sine mapping data is compressed using sine symmetry technique, sine-phase difference technique, quad line approximation technique,and quantization and error read only memory (QE-ROM) technique. The ROM size is reduced by 98% using these techniques. A compact DDFS chip with 32bit phase storage depth and a 10bit on-chip digital to analog converter has been successfully implemented using a standard 0.35μm CMOS process. The core area of the DDFS is 1.6mm^2. It consumes 167mW at 3.3V,and its spurious free dynamic range is 61dB.

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This paper proposes a novel single electron random number generator (RNG). The generator consists of multiple tunneling junctions (MTJ) and a hybrid single electron transistor (SET)/MOS output circuit. It is an oscillator-based RNG. MTJ is used to implement a high-frequency oscillator,which uses the inherent physical randomness in tunneling events of the MTJ to achieve large frequency drift. The hybrid SET and MOS output circuit is used to amplify and buffer the output signal of the MTJ oscillator. The RNG circuit generates high-quality random digital sequences with a simple structure. The operation speed of this circuit is as high as 1GHz. The circuit also has good driven capability and low power dissipation. This novel random number generator is a promising device for future cryptographic systems and communication applications.

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采用可求解可压缩流动与传热的全速度SIMPLE算法, 对低功率氩电弧加热发动机内部的传热与流动进行了数值模拟, 获得了电弧加热发动机内的温度、速度、马赫数及流线分布. 计算结果表明: 电弧加热发动机内最高温度出现在阴极下游附近中心轴线处, 这是因为电弧在阴极表面收缩形成阴极弧点, 从而焦耳热成为该高温区的主要加热机制; 沿着发动机中心轴线, 气体温度和速度开始时随着距阴极距离的增加而迅速增加, 然后在等离子体流向喷管出口的过程中, 气体温度和速度逐渐下降. 此外还详细考察了弧电流变化对电弧加热发动机内部传热与流动特性的影响, 计算获得的发动机流量和比冲与实验结果基本一致.

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椭圆曲线密码算法作为高安全性的公钥密码;ECC算法的优化和软硬件实现是当前的研究热点;采用硬件实现椭圆曲线密码算法具有速度快、安全性高的特点,随着功耗分析、旁路攻击等新型分析方法的发展,密码算法硬件实现中的低功耗设计越来越重要;针对椭圆曲线密码算法的特点,主要对该算法芯片设计中的低功耗设计方法进行探讨。

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We have observed, respectively, a negative differential resistance (NDR) and switching conduction in current-voltage (I-V) characteristics of organic diodes based on copper phthalocyanine (CuPc) film sandwiched between indium-tin-oxide (ITO) and aluminum (Al) by controlling the evaporation rate. The NDR effect is repeatable which can be well, controlled by sweep rate and start voltage, and the switching exhibits write-once-read-many-times (WORM) memory characteristics. The traps in the organic layer and interfacial dipole have been used to explain the NDR effect and switching conduction. This opens up potential applications for CuPc organic semiconductor in low power memory and logic circuits.

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The authors observed a negative differential resistance (NDR) in organic devices consisting of 9,10-bis-(9,9-diphenyl-9H-fluoren-2-yl)-anthracene (DPFA) sandwiched between Ag and indium tin oxide electrodes. The large NDR shown in current-voltage characteristics is reproducible, resulting in that the organic devices can be electrically switched between a high conductance state (on state) and a low conductance state (off state). It can be found that the currents at both on to off states are space-charge limited and attributed to the electron traps at the Ag/DPFA interface. The large and reproducible NDR makes the devices of tremendous potential in low power memory and logic circuits.