Tissue distributions and seasonal dynamics of the hepatotoxic microcystins-LR and -RR in a freshwater snail (Bellamya aeruginosa) from a large shallow, eutrophic lake of the subtropical China

Tissue distributions and seasonal dynamics of the hepatotoxic microcystins-LR and -RR in a freshwater snail (Bellamya aeruginosa) were studied monthly in a large shallow, eutrophic lake of the subtropical China during June-November, 2003. Microcystins (MCs) were quantitatively determined by High-Performance Liquid Chromatography (HPLC) with a qualitative analysis by a Finnigan LC-MS system. On the average of the study period, hepatopancreas was the highest in MC contents (mean 4.14 and range 1.06-7.42 mug g(-1) DW), followed by digestive tracts (mean 1.69 and range 0.8-4.54 mug g(-1) DW) and gonad (mean 0.715 and range 0-2.62 mug g(-1) DW), whereas foot was the least (mean 0.01 and range 0-0.06 mug g(-1) DW). There was a positive correlation in MC contents between digestive tracts and hepatopancreas. A constantly higher MC content in hepatopancreas than in digestive tracts indicates a substantial bioaccumulation of MCs in the hepatopancreas of the snail. The average ratio of MC-LR/MC-RR showed a steady increase from digestive tracts (0.44) to hepatopancreas (0.63) and to gonad (0.96), suggesting that MC-LR was more resistant to degradation in the snail. Since most MCs were present in the hepatopancreas, digestive tracts and gonad with only a very small amount in the edible foot, the risk to human health may not be significant if these toxic parts are removed prior to snail consumption. However, the possible transference of toxins along food chains should not be a negligible concern. (C) 2004 Elsevier Ltd. All rights reserved.

Growth and fabrication of AlGaN/GaN HEMT based on Si(111) substrates by MOCVD

AlGaN/GaN high electron mobility transistor (HEMT) hetero-structures were grown on the 2-in Si (1 1 1) substrate using metal-organic chemical vapor deposition (MOCVD). Low-temperature (LT) AlN layers were inserted to relieve the tension stress during the growth of GaN epilayers. The grown AlGaN/GaN HEMT samples exhibited a maximum crack-free area of 8 mm x 5 mm, XRD GaN (0 0 0 2) full-width at half-maximum (FWHM) of 661 arcsec and surface roughness of 0.377 nm. The device with a gate length of 1.4 mu m and a gate width of 60 mu m demonstrated maximum drain current density of 304 mA/mm, transconductance of 124 mS/mm and reverse gate leakage current of 0.76 mu A/mm at the gate voltage of -10 V. (C) 2008 Published by Elsevier Ltd.

High-performance 2 mm gate width GaNHEMTs on 6H-SiC with output power of 22.4 W @ 8 GHz

Optimized AlGaN/AlN/GaN high electron mobility transistors (HEMTs) structures were grown on 2-in semi-insulating (SI) 6H-SiC substrate by metal-organic chemical vapor deposition (MOCVD). The 2-in. HEMT wafer exhibited a low average sheet resistance of 305.3 Omega/sq with a uniformity of 3.85%. The fabricated large periphery device with a dimension of 0.35 pm x 2 nun demonstrated high performance, with a maximum DC current density of 1360 mA/mm, a transconductance of 460 mS/mm, a breakdown voltage larger than 80 V, a current gain cut-off frequency of 24 GHz and a maximum oscillation frequency of 34 GHz. Under the condition of continuous-wave (CW) at 9 GHz, the device achieved 18.1 W output power with a power density of 9.05 W/mm and power-added-efficiency (PAE) of 36.4%. While the corresponding results of pulse condition at 8 GHz are 22.4 W output power with 11.2 W/mm power density and 45.3% PAE. These are the state-of-the-art power performance ever reported for this physical dimension of GaN HEMTs based on SiC substrate at 8 GHz. (c) 2008 Elsevier Ltd. All rights reserved.

Resonant tunnelling diodes and high electron mobility transistors integrated on GaAs substrates

A1GaAs/1nGaAs high electron mobility transistors (HEMTs) and AlAs/GaAs resonant tunnelling diodes (RTDs) are integrated on GaAs substrates. Molecular beam epitaxy is used to grow the RTD on the HEMT structure. The current-voltage characteristics of the RTD and HEMT are obtained on a two-inch wafer. At room temperature, the peak-valley, current ratio and the peak voltage are about 4.8 and 0.44 V, respectivcly The HEMT is characterized by a, gate length of 1 mu m, a, maximum transconductance of 125 mS/mm, and a threshold voltage of -1.0 V. The current-voltage, characteristics of the series-connected RTDs are presented. Tire current-voltage curves of the parallel connection of one RTD and one HEMT are also presented.

An integrated optical receiver in MS/RF CMOS process

A monolithically integrated optoelectronic receiver was realized utilizing a deep sub-micron MS/RF CMOS process. Novel photo-diode with STI and highspeed receiver circuit were designed. This OEIC takes advantage of several new features to improve the performance.

An ambient proof and wide tuning range LC VCO with automatic amplitude control for tuner applications

This paper represents a LC VCO with AAC (Auto Amplitude Control), in which PMOS FETs are used as active components, and the varactors are directly connected to ground to widen Kvco linear range. The AAC circuitry adds little noise to the VCO and provides it with robust performance over a wide temperature and carrier frequency range. The VCO is fabricated in 50-GHz 0.35-mu m SiGe BiCMOS process. The measurement results show that it has -127.27-dBc/Hz phase noise at 1-MHz offset and a linear gain of 32.4-MHz/V between 990-MHz and 1.14-GHz. The whole circuit draws 6.6-mA current from 5.0-V supply.

A Smart Frequency Presetting Technique for Fast Lock-in LC-PLL Frequency Synthesizer

This paper proposes a smart frequency presetting technique for fast lock-in LC-PLL frequency synthesizer. The technique accurately presets the frequency of VCO with small initial frequency error and greatly reduces the lock-in time. It can automatically compensate preset frequency variation with process and temperature. A 2.4GHz synthesizer with 1MHz reference input was implemented in 0.35 mu m CMOS process. The chip core area is 0.4mm(2). Output frequency of VCO ranges from 2390 to 2600MHz. The measured results show that the typical lock-in time is 3 mu s. The phase noise is -112dBc/Hz at 600KHz offset from center frequency. The test chip consumes current of 22mA that includes the consumption of the I/O buffers.

ICP-OES的悬浮进样方式及ICP-MS的碰撞/反应池技术的研究与应用

本论文分为两部分：1. 综述部分（第一章和第二章），评述了悬浮进样方式在电感耦合等离子体发射光谱法（ICP-OES）中的研究与应用；电感耦合等离子体质谱（ICP-MS）中碰撞/反应池技术研究的新进展。2. 实验部分（第三章至第九章），内容包括针对不同性质的样品悬浮液选择适当的稳定剂和悬浮雾化ICP-OES的校准方法研究；以混合碰撞/反应气体解决难度较大的高纯氧化钕中稀土杂质测定的干扰问题；以及浊点萃取-石墨炉原子吸收法测定环境样品中痕量镉、氢化物发生-原子荧光光谱法测定铅基合金中砷和植物样品中锗等实用性强的分析方法研究。 ICP的传统进样方式是将样品转化成水溶液形式，以溶液方式进样。然而大多数样品是以固态形式存在，许多样品相当难溶或难熔。采用直接固体进样方法对这些样品进行分析，是分析工作者追求的目标之一。悬浮液进样是一种固体直接进样方法，除了具有其它固体进样技术的优点外，其最大优点是可以像溶液雾化一样用标准水溶液校准。本研究针对实际分析工作中遇到的具体样品，对悬浮进样ICP-OES技术进行了比较深入的研究，成功解决了样品处理繁琐和样品难以处理等困难。对特殊地质样品和激光晶体材料（Nd:YAG）的悬浮进样分析进行了探索。主要工作为：①建立分析地质样品中主量和微量元素的方法，标准水溶液可以成功地用于校准。优点是可以同时对地质样品中的Si和其它元素进行分析，避免了传统分析时需分别处理样品的麻烦。②探索了分析铌钽矿中铌和钽的应用。由于铌和钽具有强抗化学腐蚀性，所以溶液进样分析时样品处理过程复杂。结果表明，以标准水溶液校准时，只要样品研磨时间延长至5 h，即可获得悬浮进样的满意的回收率。③研究了分析掺钕钇铝石榴石(Nd:YAG)中钕掺杂量的可行性。研究表明，加入适量聚丙烯酸作分散剂并调节pH为6，可以得到稳定悬浮液；以通用标准加入法（GSAM）校准可以得到满意的结果。 我国的稀土资源占世界的80％以上，高纯稀土氧化物是高科技领域中的重要材料。碰撞/反应池技术是目前四极杆ICP-MS消除干扰的先进技术，可以选择性地减少某些基体干扰，使背景和检测限得到显著的改进。本实验选择氧化钕（有7个同位素）作为研究对象，采用碰撞/反应池技术重点解决四极杆ICP-MS方法对高纯Nd2O3中稀土杂质进行测定时，基体Nd对Tb、Dy和Ho严重的氧化物或氢氧化物干扰难题。研究结果如下：①在四极杆高分辨率模式下，可以消除Nd对Pr的相邻峰的拖尾干扰；②采用碰撞/反应池技术，设计了10% O2-10% Ar-80% He混合气体作为碰撞/反应气，将Tb、Dy和Ho分别转化为相应的氧化物离子进行测定，成功地消除了基体Nd对Ho的干扰；Nd对Tb和Dy造成干扰的表观浓度显著降低。本方法可直接测定纯度为6N的高纯Nd2O3中的Ho；对纯度为6N的高纯Nd2O3中的Tb和Dy进行扣除，可以分析纯度达5N的高纯Nd2O3中的Tb和Dy。与文献报道的其它消除基体Nd干扰的方法相比较，此方法能够对纯度更高的Nd2O3进行直接分析，且操作简便。此方法也可进一步拓宽，有望解决其它轻稀土氧化物对中重稀土检测的质谱干扰问题。 论文的7～9章的工作包括：浊点萃取-GFAAS测定环境样品中痕量镉、HG-AFS分析铅基合金中砷和植物样品中锗的研究。针对实际分析工作中的具体困难，以上工作分别解决了分析元素含量低、测定干扰严重及样品处理的问题，建立了实用性强、准确度高的分析方法，具有实际应用价值。

免疫球蛋白的制备及其质谱研究

用狂犬病毒免疫产蛋鸡，获得的免疫卵黄经水稀释脱脂－两步盐析－凝胶过滤法分离，得到的IgY经SDS－PAGE分析其纯度在98％以上。纯化的 IgY 经二硫苏糖醇（DTT）还原，得到重链 (HC) 和轻链 (LC)。另外，IgY 经胃蛋白酶（pH4.0, 37℃）酶解后，得到片断抗体Fab。采用 MALDI-MS手段较准确地测定了 IgY及HC, LC, Fab的平均分子量，分别为 167250Da, 65105Da, 18660Da 和 45359Da，测量误差在 0.2%以下。研究表明，和哺乳动物的 IgGs相比，鸡卵黄 IgY的结构有两个特点：1．它的重链较长而轻链较短；2．胃蛋白酶敏解后产生 Fab而不是 F(ab')_2。对抗幽门螺杆菌 IgY 的研究表明，鸡卵黄免疫球蛋白具有良好的稳定性。在热、酸、胃蛋白酶和胰蛋白酶处理的条件下，IgY能够保留大部分抗体活性。免疫亲和捕获和 MALDI-MS手段相结合产生了免疫和质谱技术。我们在研究中发展了这一技术，提出了一个简单而有效的免疫分析方法。以干扰素－抗干扰素单抗为模型，确定了混合物中抗原蛋白质的存在，确定了抗原蛋白质上与抗体结合的大致位点。在MALDI-MS测定蛋白质分子量的实验中，采用了在线纯化蛋白质样品的新技术，简单、快速，能够提高蛋白质分子量测定的灵敏度，各种离子的信噪比和丰度得到改善。笼内金属富勒烯的有效提取对于进一步深入研究它的各种性质至关重要。采用高温高压法有效地提取了烟炱中的笼内金属富勒烯 M@C_(82) (M=Y, La, Gd, Tb)，选择的提取溶剂为 1,2,4-三氯苯，金属富勒烯的产率较高，为烟炱的0.5%。

A 10-bit 50-MS/s sample-and-hold circuit with low distortion sampling switches

A fully-differential switched-capacitor sample-and-hold (S/H) circuit used in a 10-bit 50-MS/s pipeline analog-to-digital converter (ADC) was designed and fabricated using a 0.35-μm CMOS process. Capacitor fliparound architecture was used in the S/H circuit to lower the power consumption. In addition, a gain-boosted operational transconductance amplifier (OTA) was designed with a DC gain of 94 dB and a unit gain bandwidth of 460 MHz at a phase margin of 63 degree, which matches the S/H circuit. A novel double-side bootstrapped switch was used, improving the precision of the whole circuit. The measured results have shown that the S/H circuit reaches a spurious free dynamic range (SFDR) of 67 dB and a signal-to-noise ratio (SNR) of 62.1 dB for a 2.5 MHz input signal with 50 MS/s sampling rate. The 0.12 mm~2 S/H circuit operates from a 3.3 V supply and consumes 13.6 mW.

MS/RF CMOS工艺兼容的光电探测器模拟与测试

设计了一种新型的与MS/RF CMOS工艺全兼容、带深n阱(DNW)、浅沟槽隔离(STI)的双光电探测器,分析了其工作机理,用器件模拟软件ATLAS对其暗电流、响应电流、光调制频率响应和波长响应进行了模拟.采用TSMC 0.18 μm MS/RF CMOS工艺进行了流片,对芯片进行了暗电流和响应度的测试.模拟和测试结果均表明,该探测器与常规双光电探测器相比,具有较低的暗电流和较高的响应度.

A 1.1GHz LC VCO with Automatic Amplitude Control for Tuner Applications

This paper presents an LC VCO with auto-amplitude control （AAC）, in which pMOS FETs are used,and the varactors are directly connected to ground to widen the linear range of Kvco. The AAC circuitry adds little noise to the VCO but provides it with robust performance over a wide temperature and carrier frequency range.The VCO is fabricated in a chartered 50GHz 0.35μm SiGe BiCMOS process. The measurements show that it has - 127. 27dBc/Hz phase noise at 1MHz offset and a linear gain of 32.4MHz/V between 990MHz and 1.14GHz.The whole circuit draws 6. 6mA current from 5V supply.