IMPROVEMENT OF STRUCTURAL INSTABILITY OF THE ION-SENSITIVE FIELD-EFFECT TRANSISTOR (ISFET)

Three causes involved in the instability of the ISFET are proposed in this study. First, it is ascertained that hydroxyl group resident at the surface of the Si3N4 film or in the electrolyte solution is most active and subject to gain or loss of electrons. This is one of the main causes for ISFET structural instability. Secondly, the stability of the pH-sensitive FET varies with deposition conditions in the fabrication process of the ISFET. This proves to be another cause of ISFET instability. Thirdly, the pH of the measured solution varies with the measuring process and time, contributing to the instability, but is not a cause of the instability of the pH-ISFET itself. We utilized the technique of readjusting and controlling the ratio of hydroxyl groups to amine groups to enhance the stability of the ISFET. Our techniques to improve stability characteristics proved to be effective in practice.

A novel noise optimization technique for inductively degenerated CMOS LNA

This paper proposes a novel noise optimization technique. The technique gives analytical formulae for the noise performance of inductively degenerated CMOS low noise amplifier (LNA) circuits with an ideal gate inductor for a fixed bias voltage and nonideal gate inductor for a fixed power dissipation, respectively, by mathematical analysis and reasonable approximation methods. LNA circuits with required noise figure can be designed effectively and rapidly just by using hand calculations of the proposed formulae. We design a 1.8 GHz LNA in a TSMC 0.25 pan CMOS process. The measured results show a noise figure of 1.6 dB with a forward gain of 14.4 dB at a power consumption of 5 mW, demonstrating that the designed LNA circuits can achieve low noise figure levels at low power dissipation.

1-Gb/s zero-pole cancellation CMOS transimpedance amplifier for Gigabit Ethernet applications

A zero-pole cancellation transimpedance amplifier (TIA) has been realized in 0.35 μm RF CMOS tech nology for Gigabit Ethernet applications. The TIA exploits a zero-pole cancellation configuration to isolate the input parasitic capacitance including photodiode capacitance from bandwidth deterioration. Simulation results show that the proposed TIA has a bandwidth of 1.9 GHz and a transimpedance gain of 65 dB·Ω for 1.5 pF photodiode capaci tance, with a gain-bandwidth product of 3.4 THz·Ω. Even with 2 pF photodiode capacitance, the bandwidth exhibits a decline of only 300 MHz, confirming the mechanism of the zero-pole cancellation configuration. The input resis tance is 50 Ω, and the average input noise current spectral density is 9.7 pA/(Hz)~(1/2). Testing results shows that the eye diagram at 1 Gb/s is wide open. The chip dissipates 17 mW under a single 3.3 V supply.

低温漂高电源抑制的CMOS片上电流源

设计了一种用于驱动电路和模数转换器的片上电流源,该结构利用带隙基准的方法产生了一个与温度无关的参考电平,同时为了满足高电源抑制的要求,电流源中采用了运算放大器的负反馈环路来抑制电源到输出的增益,从而使输出电平与电源电压无关,然后通过电阻把电压转化为电流.该电路在0.35,μm、3.3 V的工艺下实现,芯片面积为0.03 mm~2.仿真和测试结果表明,该电流源的温度系数为8.7×10~(-6)/℃,在2.6～4 V的电源电压下均能正常工作,达到了系统要求.

与CMOS兼容的硅基波导型光电探测器的研究

硅基波导型光电探测器作为一类重要的光电探测器,由于其能与标准的CMOS工艺兼容以及制备工艺简单等性能,因而在光电子单片集成方面具备广阔的市场应用前景.文章着重阐述了通过离子注入引入深能级、Ge/Si自组装岛、SOI波导共振腔增强和AlGaInAs-Si混合集成等四种方式来制备硅基光电探测器的研究现状和研究进展,并对四类器件的结构,制作工艺和光电性能指标进行了详细地介绍.