A widely tunable continuous-time LPF for a direct conversion DBS Tuner

A continuous-time 7th-order Butterworth Gm-C low pass filter (LPF) with on-chip automatic tuning circuit has been implemented for a direct conversion DBS tuner in a 0.35um SiGe BiCMOS technology. The filter's -3dB cutoff frequency f(0) can be tuned from 4MHz to 40MHz. A novel translinear transconductor (Gm) cell is used to implement the widely tunable and high linear filter. The filter has -0.5dB passband gain, 28nV/Hz(1/2) input referred noise, -2dBVrms passband IIP3, 24dBVrms stopband IIP3. The I/Q LPFs with the tuning circuit draw 16mA (with f(0)=20MHz) from 3.3 V supply, and occupy an area of 0.45 mm(2).

Neuro-Stimulus Chip with Photodiodes Array for Sub-retinal Implants

A prototype neuro-stimulus chip for sub-retinal implants in blind patients affected by Age-related Macular Degeneration (AMD) or Retinitis Pigmentosa (RP) is presented in this paper. This retinal prosthetic chip was designed to replace the degenerated photoreceptor cells, and in order to stimulate directly the remaining healthy layers of retinal neurons. The current stimulus circuits are monolithic integrated with photodiodes (PD) array, which can convert the illumination on the eyes into bi-phasic electrical pulses. In addition, a novel charge cancellation circuit is used to discharge the electrodes for medical safty. The prototype chip is designed and fabricated in HJTC 0.18 mu m N-well CMOS 1P6M Mix-signal process, with a +/- 2.5 V dual voltage power supply.

A Compact Direct Digital Frequency Synthesizer for System-on-chip

A compact direct digital frequency synthesizer (DDFS) for system-on-chip (SoC) is developed in this paper. For smaller chip size and lower power consumption, the phase to sine mapping data is compressed by using sine symmetry technique, sine-phase difference technique, quad line approximation (QLA) technique and quantization and error read only memory (QE-ROM) technique. The ROM size is reduced by 98 % using the techniques mentioned above. A compact DDFS chip with 32-bit phase storage depth and a 10-bit on-chip digital to analog converter(DAC) has been successfully implemented using standard 0.35um CMOS process. The core area of the DDFS is 1.6mm(2). It consumes 167 mW at 3.3V, and its spurious free dynamic range (SFDR) is 61dB.

A Fast-Locking Phase-Locked Loop Using a Seven-State Phase Frequency Detector

A seven-state phase frequency detector (S.S PFD) is proposed for fast-locking charge pump based phase-locked loops (CPPLLs) in this paper. The locking time of the PLL can be significantly reduced by using the seven-state PFD to inject more current into the loop filter. In this stage, the bandwidth of the PLL is increased or decreased to track the phase difference of the reference signal and the feedback signal. The proposed architecture is realized in a standard 0.35 mu m 2P4M CMOS process with a 3.3V supply voltage. The locking time of the proposed PLL is 1.102 mu s compared with the 2.347 mu s of the PLL based on continuous-time PFD and the 3.298 mu s of the PLL based on the pass-transistor tri-state PFD. There are 53.05% and 66.59% reductions of the locking time. The simulation results and the comparison with other PLLs demonstrate that the proposed seven-state PFD is effective to reduce locking time.

Design and Verification of the Programming Circuit in an Application-Specific FPGA

In this paper we present a methodology and its implementation for the design and verification of programming circuit used in a family of application-specific FPGAs that share a common architecture. Each member of the family is different either in the types of functional blocks contained or in the number of blocks of each type. The parametrized design methodology is presented here to achieve this goal. Even though our focus is on the programming circuitry that provides the interface between the FPGA core circuit and the external programming hardware, the parametrized design method can be generalized to the design of entire chip for all members in the FPGA family. The method presented here covers the generation of the design RTL files and the support files for synthesis, place-and-route layout and simulations. The proposed method is proven to work smoothly within the complete chip design methodology. We will describe the implementation of this method to the design of the programming circuit in details including the design flow from the behavioral-level design to the final layout as well as the verification. Different package options and different programming modes are included in the description of the design. The circuit design implementation is based on SMIC 0.13-micron CMOS technology.

A Novel Low-Power Digital Baseband Circuit for UHF RFID Tag with Sensors

A novel low-power digital baseband circuit for UHF RFID tag with sensors is presented in this paper. It proposes a novel baseband architecture and a new operating scheme to fulfill the sensor functions and to reduce power consumption. It is also compatible with the EPC C1G2 UHF RFID protocol. It adopts some advanced low power techniques for system design and circuit design: adaptive clock-gating, multi-clock domain and asynchronous circuit. The baseband circuit is implemented in 0.18um 1P3M standard CMOS process. ne chip area is 0.28 mm(2) excluding test pads. Its power consumption is 25uW under 1.1V power supply.

A Synthesis Tool for a Tile-Based Heterogeneous FPGA

A multi-mode logic cell architecture in a tile-based heterogeneous FPGA is proposed, and a logic synthesis tool, called Vsyn, based on this architecture is presented. The logic cell architecture design and its synthesis tool development are strongly influencing each other. Any feature or parameter from one needs to be fully exercised and verified on the other. In this paper, we presented experimental results based MCNC benchmarks to show that the integration of the synthesis tool and the FPGA architecture can achieve high performance in the targeted FPGA applications. In addition, Vsyn can also target embedded special-purpose macros for the heterogeneous FPGA.

In-situ Boron-doped Low-stress LPCVD Polysilicon for Micromechanical Disk Resonator

Polycrystalline silicon (polysilicon) has been used as an important structural material for microelectro-mechnical systems (MEMS) because of its compatibility with standard integrated circuit (IC) processes. As the structural layer of micromechanical high resonance frequency (high-f) and high quality factor (high-Q) disk resonators, the low residual stress and low resistivity are desired for the polysilicon thin films. In the present work, we investigate the effect of deposition and annealing conditions on the residual stress and resistivity for in-situ deposited low pressure chemical vapor deposition (LPCVD) polysilicon films. Low residual stress (-100 MPa) was achieved in in-situ boron-doped polysilicon films deposited at 570 degrees C and annealed at 1000 degrees C for 4 hr. The as-deposited amorphous polysilicon films were crystallized by the rapid thermal annealing and have the (111)-preferred orientation, the low tensile residual stress is expected for this annealed film, the detailed description on this work will be reported soon. The controllable residual stress and resistivity make these films suitable for high-Q and bigh-f micro-mechanical disk resonators.

Simulation and fabrication of the SiC-based clamped-clamped filter

In this paper, the SiC-based clamped-clamped filter was designed and fabricated. The filter was composed of two clamped-clamped beam micromechanical resonators coupled by a spring coupling beam. Structural geometries, including the length and width of the resonator beam and coupling beam, were optimized by simulation for high frequency and high Q, under the material properties of SiC. The vibrating modes for the designed filter structure were analyzed by finite element analysis (FEA) method. For the optimized structure, the geometries of resonator beams and coupling beams, as well as the coupling position, the SiC-based clamped-clamped filter was fabricated by surface micromaching technology.

High-quality-factor EH modes in microcylinder resonators predicted by 3D FDTD simulation

The mode characteristis of a microcylinders with center layer thickness 0.2 mu m and radius 1 mu m are investigated by the three-dimensional (31)) finite-difference time-domain (FDTD) technique and the Pade approximation. The mode quality factor (Q-factor) of the EH71 mode obtained by 3D FDTD increase with the increase of the refractive index of the cladding layer n(2) as n(2) smaller than 3.17, and can be as large as 2.4 x 10(4) as the vertical refractive index distribution is 3.17/3.4/3.17, which is much larger than that of the HE71 mode with the same vertical refractive index distribution.

Growth mechanism of InGaAlAs waveguides by narrow stripe selective MOVPE

Growth mechanism of InGaAlAs waveguides by narrow stripe selective MOVPE has been studied. Both the InGaAlAs bulk waveguides and the InGaAlAs MQW waveguides were successful grown on the patterned substrates at optimized growth conditions. The mask stripe width varied from 0 to 40 mu m, while the window region width between a pair of mask stripes was fixed 2.5 mu m. These selectively grown waveguides were covered by specific InP layers, which can keep the InGaAlAs waveguides from being oxidized during the fabrication of devices. In particular, there exhibit strong dependences of the photoluminescence (PL) spectrum on the mask stripe width for the samples. The results were explained in considering both the migration effect from a masked region (MMR) and the lateral vapor diffusion effect (LVD).

Anomalous temperature-dependent bimodal size evolution of InAs quantum dots on vicinal GaAs(100) substrates

Temperature-dependent bimodal size evolution of InAs quantum dots on vicinal GaAs(100) substrates grown by metalorganic chemical vapor deposition (MOCVD) is studied. An abnormal trend of the evolution on temperature is observed. With the increase of the growth temperature, while the density of the large dots decreases continually, that of the small dots first grows larger when temperature was below 520 degrees C, and then there is a sudden decrease at 535 degrees C. Photoluminescence (PL) studies show that QDs on vicinal substrates have a narrower PL line width, a longer emission wavelength and a larger PL intensity.

Simulation of a monolithically integrated CMOS bioamplifier for EEG recordings

A monolithically integrated CMOS bioamplifier is presented in this paper for EEG recording applications. The capacitive-coupled circuit input structure is utilized to eliminate the large and random DC offsets existing in the electrode-tissue interface. Diode-connected NMOS transistors with negative voltage between gate and source are candidates for large resistors necessary to the bioamplifier. A passive BEF (Band Eliminator Filter) can reduce 50 Hz noise disturbance strength by more than 60 dB. A novel analysis approach is given to help determine the noise power spectral density. Simulation results show that the two-stage CMOS bioamplifier in a closed-loop capacitive feedback configuration,provides an AC in-band gain of 39.6 dB, a DC gain of zero, and an input-referred noise of 87 nVrms integrated from 0.01 Hz to 100 Hz.

A standard CMOS compatible monolithic photo-detector and trans-impedance amplifier

A 1GHz monolithic photo-detector (PD) and trans-impedance amplifier (TIA) is designed with the standard 0.35 mu m CMOS technique. The design of the photo-detector is analyzed and the CMOS trans-impedance amplifier is also analyzed in the paper. The integrating method is described too. The die photograph is also showed in the paper.

A two-step backoff scheme for improving the performance of the IEEE 802.11 distributed coordination function

This paper describes the binary exponential backoff mechanism of 802.11 distributed coordination function (DCF), and introduces some methods of modifying the backoff scheme. Then a novel backoff scheme, called Two-step Backoff scheme, is presented and illustrated. The simulation process in OPNET environment has been described also. At last, the analysis and simulation results show that the Two-step backoff scheme can enhance the performance of the IEEE 802.11 DCF.