84 resultados para Design and Analysis of Compute Experiment (DACE)
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Origin of polarization sensitivity of photonic wire waveguides (PWWs) is analysed and the effective refractive indices of two different polarization states are calculated by the three-dimensional full-vector beam propagation method. We find that PWWs are polarization insensitive if the distribution of its refractive index is uniform and the cross section is square. An MRR based on such a polarization-insensitive PWW is fabricated on an 8-inch silicon-on-insulator wafer using 248-nm deep ultraviolet lithography and reactive ion etching. The quasi-TE mode is resonant at 1542.25 nm and 1558.90 nm, and the quasi-TM mode is resonant at 1542.12 nm and 1558.94 nm. The corresponding polarization shift is 0.13 nm at the shorter wavelength and 0.04 nm at the longer wavelength. Thus the fabricated device is polarization independent. The extinction ratio is larger than 10 dB. The 3 dB bandwidth is about 2.5 nm and the Qvalue is about 620 at 1558.90 nm.
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AlGaN-based resonant-cavity-enhanced (RCE) p-i-n photodetectors (PDs) for operating at the wavelength of 330 nm were designed and fabricated. A 20.5-pair AlN/Al0.3Ga0.7N distributed Bragg reflector (DBR) was used as the back mirror and a 3-pair AlN/Al0.3Ga0.7N DBR as the front one. In the cavity is a p-GaN/i-GaN/n-Al0.3Ga0.7N structure. The optical absorption of the RCE PD structure is at most 59.8% deduced from reflectance measurement. Selectively enhanced by the cavity effect, a response peak of 0.128 A/W at 330 nm with a half-peak breadth of 5.5 nm was obtained under zero bias. The peak wavelength shifted 15 nm with the incident angle of light increasing from 0 degrees to 60 degrees.
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We report on the design and fabrication of a photonic crystal (PC) channel drop filter based on an asymmetric silicon-on-insulator (SOI) slab. The filter is composed of two symmetric stick-shape micro-cavities between two single-line-defect (W1) waveguides in a triangular lattice, and the phase matching condition for the filter to improve the drop efficiency is satisfied by modifying the positions and radii of the air holes around the micro-cavities. A sample is then fabricated by using electron beam lithography (EBL) and inductively coupled plasma (ICP) etching processes. The measured 0 factor of the filter is about 1140, and the drop efficiency is estimated to be 73% +/- 5% by fitting the transmission spectrum.
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An efficient polarization splitter based on a microracetrack resonator in silicon-on-insulator has been designed and realized using electron beam lithography and inductively coupled plasma etching. Polarization-dependent waveguides and the microracetrack resonator are combined and exploited to split two orthogonal polarizations. Rib waveguides are employed to enhance the coupling efficiency for the transverse-electric mode and endow the resonator with high performance for both polarizations. In experiments, a splitting ratio has been achieved of about 20 dB at the drop port around 1550 nm for each extracted polarization, in good agreement with the prediction.
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A folding nonblocking 4 X 4 optical matrix switch in simplified-tree architecture was designed and fabricated on a silicon-on-insulator wafer. To compress chip size, switch elements (SEs) were connected by total internal reflection mirrors instead of conventional S-bends. For obtaining smooth interfaces, potassium hydroxide (KOH) anisotropic chemical etching of silicon was employed. The device has a compact size of 20 X 3.2 mm(2) and a fast response of 8 +/- 1 mu s. Power consumption of 2 x 2 SE and excess loss per mirror were 145 mW and -1.1 dB, respectively. (c) 2005 Society of Photo-Optical Instrumentation Engineers.
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A low power consumption 2 x 2 thermo-optic switch with fast response was fabricated on silicon-on-insulator by anisotropy chemical etching. Blocking trenches were etched on both sides of the phase-shifting arms to shorten device length and reduce power consumption. Thin top cladding layer was grown to reduce power consumption and switching time. The device showed good characteristics, including a low switching power of 145 mW and a fast switching speed of 8 +/- 1 mus, respectively. Two-dimensional finite element method was applied to simulate temperature field in the phase-shifting arm instead of conventional one-dimensional method. According to the simulated result, a new two-dimensional index distribution of phase-shifting arm was determined. Consequently finite-difference beam propagation method was employed to simulate the light propagation in the switch, and calculate the power consumption as well as the switching speed. The experimental results were in good agreement with the theoretical estimations. (C) 2004 Elsevier B.V. All rights reserved.
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National High Technology Research and Development Program of China 2007AA03Z112;Program of Ministry of Education of China 20060183030;Program of Jilin Provincial Science and Technology Department of China 20070709;Program of Bureau of Science and Technology of Changchun City 2007107
Resumo:
A resonant-cavity enhanced reflective optical modulator is designed and frabricated, with three groups of three highly strained InGaAS/GaAs quantum wells in the cavity, for the low voltage and high contrast ratio operation. The quantum wells are positioned in antinodes of the optical standing wave. The modulator is grown in a single growth step in an molecular beam epitaxy system, using GaAs/AIAs distributed Bragg reflectors as both the top and bottom mirrors. Results show that the reflection device has a modulation extinction of 3 dB at -4.5 V bias.
Resumo:
This paper introduces a complete CAD toolset for the implementation of digital logic in a Field-Programmable Gate Array (FPGA) platform. Compared with existing academic toolsets, this toolset introduces formal verification in each step of the tool flow, especially the formal verification of the configuration bitstream. The FPGA CAD tool verification flow using Formality is presented in detail. Using plug-in technology, we have developed an integrated FPGA design kit to incorporate all tools together.
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Under high concentration the temperature of photovoltaic solar cells is very high. It is well known that the efficiency and performance of photovoltaic solar cells decrease with the increase of temperature. So cooling is indispensable for a concentrator photovoltaic solar cell at high concentration. Usually passive cooling is widely considered in a concentrator system. However, the thermal conduction principle of concentrator solar cells under passive cooling is seldom reported. In this paper, GaInP/GaAs/Ge triple junction solar cells were fabricated using metal organic chemical vapor deposition technique. The thermal conductivity performance of monolithic concentrator GaInP/GaAs/Ge cascade solar cells under 400X concentration with a heat sink were studied by testing the surface and backside temperatures of solar cells. The tested result shows that temperature difference between both sides of the solar cells is about 1K. A theoretical model of the thermal conductivity and thermal resistance of the GaInP/GaAs/Ge triple junction solar cells was built, and the calculation temperature difference between both sides of the solar cells is about 0.724K which is consistent with the result of practical test. Combining the theoretical model and the practical testing with the upper surface temperature of tested 310K, the temperature distribution of the solar cells was researched.
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The measurement and analysis of the microwave frequency response of semiconductor optical amplifiers (SOAs) are proposed in this paper. The response is measured using a vector network analyzer. Then with the direct-subtracting method, which is based on the definition of scattering parameters of optoelectronic devices, the responses of both the optical signal source and the photodetector are eliminated, and the response of only the SOA is extracted. Some characteristics of the responses can be observed: the responses are quasi-highpass; the gain increases with the bias current; and the response becomes more gradient while the bias current is increasing. The multisectional model of an SOA is then used to analyze the response theoretically. By deducing from the carrier rate equation of one section under the steady state and the small-signal state, the expression of the frequency response is obtained. Then by iterating the expression, the response of the whole SOA is simulated. The simulated results are in good agreement with the measured on the three main characteristics, which are also explained by the deduced results. This proves the validity of the theoretical analysis.
Resumo:
In this paper we present a methodology and its implementation for the design and verification of programming circuit used in a family of application-specific FPGAs that share a common architecture. Each member of the family is different either in the types of functional blocks contained or in the number of blocks of each type. The parametrized design methodology is presented here to achieve this goal. Even though our focus is on the programming circuitry that provides the interface between the FPGA core circuit and the external programming hardware, the parametrized design method can be generalized to the design of entire chip for all members in the FPGA family. The method presented here covers the generation of the design RTL files and the support files for synthesis, place-and-route layout and simulations. The proposed method is proven to work smoothly within the complete chip design methodology. We will describe the implementation of this method to the design of the programming circuit in details including the design flow from the behavioral-level design to the final layout as well as the verification. Different package options and different programming modes are included in the description of the design. The circuit design implementation is based on SMIC 0.13-micron CMOS technology.
Resumo:
We report on the design and fabrication of a photonic crystal (PC) channel drop filter based on an asymmetric silicon-on-insulator (SOI) slab. The filter is composed of two symmetric stick-shape micro-cavities between two single-line-defect (W1) waveguides in a triangular lattice, and the phase matching condition for the filter to improve the drop efficiency is satisfied by modifying the positions and radii of the air holes around the micro-cavities. A sample is then fabricated by using electron beam lithography (EBL) and inductively coupled plasma (ICP) etching processes. The measured 0 factor of the filter is about 1140, and the drop efficiency is estimated to be 73% +/- 5% by fitting the transmission spectrum.
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zhangdi于2010-03-29批量导入
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Optoelectronic packaging has become a most important factor that influences the final performance and cost of the module. In this paper, low microwave loss coplanar waveguide(CPW) on high resistivity silicon(HRS) and precise V groove in silicon substrate were successfully fabricated. The microwave attenuation of the CPW made on HRS with the simple process is lower than 2 dB/cm in the frequency range of 0 similar to 26GHz, and V groove has the accuracy in micro level and smooth surface. These two techniques built a good foundation for high frequency packaging and passive coupling of the optoelectronic devices. Based on these two techniques, a simple high resistivity silicon substrate that integrated V groove and CPW for flip-chip packaging of lasers was completed. It set a good example for more complicate optoelectronic packaging.