采用标准CMOS工艺制作的叉指型结构硅发光二极管

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基于标准CMOS工艺的积分电容及其制作方法

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一种采用CMOS工艺制作的差分硅光电探测器

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SOI衬底CMOS工艺电光调制器

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A low-cost CMOS programmable temperature

A novel uncalibrated CMOS programmable temperature switch with high temperature accuracy is presented. Its threshold temperature T-th can be programmed by adjusting the ratios of width and length of the transistors. The operating principles of the temperature switch circuit is theoretically explained. A floating gate neural MOS circuit is designed to compensate automatically the threshold temperature T-th variation that results form the process tolerance. The switch circuit is implemented in a standard 0.35 mu m CMOS process. The temperature switch can be programmed to perform the switch operation at 16 different threshold temperature T(th)s from 45-120 degrees C with a 5 degrees C increment. The measurement shows a good consistency in the threshold temperatures. The chip core area is 0.04 mm(2) and power consumption is 3.1 mu A at 3.3V power supply. The advantages of the temperature switch are low power consumption, the programmable threshold temperature and the controllable hysteresis.

Influence of V/III ratio on the structural and photoluminescence properties of In0.52AlAs/In0.53GaAs metamorphic high electron mobility transistor grown by molecular beam epitaxy

A series of metamorphic high electron mobility transistors (MMHEMTs) with different V/III flux ratios are grown on GaAs (001) substrates by molecular beam epitaxy (XIBE). The samples are analysed by using atomic force microscopy (AFM), Hall measurement, and low temperature photoluminescence (PL). The optimum V/III ratio in a range from 15 to 60 for the growth of MMHEMTs is found to be around 40. At this ratio, the root mean square (RMS) roughness of the material is only 2.02 nm; a room-temperature mobility and a sheet electron density are obtained to be 10610.0cm(2)/(V.s) and 3.26 x 10(12)cm(-2) respectively. These results are equivalent to those obtained for the same structure grown on InP substrate. There are two peaks in the PL spectrum of the structure, corresponding to two sub-energy levels of the In0.53Ga0.47 As quantum well. It is found that the photoluminescence intensities of the two peaks vary with the V/III ratio, for which the reasons are discussed.

Properties of AlyGa1-yN/AlxGa1-xN/AlN/GaN Double-Barrier High Electron Mobility Transistor Structure

Electrical properties of AlyGa1-yN/AlxGa1-xN/AlN/GaN structure are investigated by solving coupled Schrodinger and Poisson equation self-consistently. Our calculations show that the two-dimensional electron gas (2DEG) density will decrease with the thickness of the second barrier (AlyGa1-yN) once the AlN content of the second barrier is smaller than a critical value y(c), and will increase with the thickness of the second barrier (AlyGa1-yN) when the critical AlN content of the second barrier y(c) is exceeded. Our calculations also show that the critical AlN content of the second barrier y(c) will increase with the AlN content and the thickness of the first barrier layer (AlxGa1-xN).

Quantum mechanical simulation of nanosized metal-oxide-semiconductor field-effect transistor using empirical pseudopotentials: A comparison for charge density occupation methods

The atomistic pseudopotential quantum mechanical calculations are used to study the transport in million atom nanosized metal-oxide-semiconductor field-effect transistors. In the charge self-consistent calculation, the quantum mechanical eigenstates of closed systems instead of scattering states of open systems are calculated. The question of how to use these eigenstates to simulate a nonequilibrium system, and how to calculate the electric currents, is addressed. Two methods to occupy the electron eigenstates to yield the charge density in a nonequilibrium condition are tested and compared. One is a partition method and another is a quasi-Fermi level method. Two methods are also used to evaluate the current: one uses the ballistic and tunneling current approximation, another uses the drift-diffusion method. (C) 2009 American Institute of Physics. [doi:10.1063/1.3248262]

Single-electron multiple-valued memory using ultra-small floating gate metal-oxide-semiconductor field effect transistor

This paper proposes a novel single-electron multiple-valued memory. It is a metal-oxide-semiconductor field effect transistor (MOS)-type memory with multiple separate control gates and floating gate layer, which consists of nano-crystal grains. The electron can tunnel among the grains (floating gates) and between the floating gate layer and the MOS channel. The memory can realize operations of 'write', 'store' and 'erase' of multiple-valued signals exceeding three values by controlling the single electron tunneling behavior. We use Monte Carlo method to simulate the operation of single-electron four-valued memory. The simulation results show that it can operate well at room temperature.

In situ doping control for growth of n-p-n Si/SiGe/Si heterojunction bipolar transistor by gas source molecular beam epitaxy

N-p-n Si/SiGe/Si heterostructures have been grown by a disilane (Si2H6) gas and Ge solid sources molecular beam epitaxy system using phosphine (PH3) and diborane (B2H6) as n- and p-type in situ doping sources, respectively. Adopting an in situ doping control technology, the influence of background B dopant on the growth of n-Si emitter layer was reduced, and an abrupt B dopant distribution from SiGe base to Si emitter layer was obtained. Besides, higher n-type doping in the surface region of emitter to reduce the emitter resist can be realized, and it did not result in the drop of growth rate of Si emitter layer in this technology. (C) 2004 Elsevier B.V. All rights reserved.

A novel vision chip for high-speed target tracking

This paper presents a novel vision chip for high-speed target tracking. Two concise algorithms for high-speed target tracking are developed. The algorithms include some basic operations that can be used to process the real-time image information during target tracking. The vision chip is implemented that is based on the algorithms and a row-parallel architecture. A prototype chip has 64 x 64 pixels is fabricated by 0.35 pm complementary metal-oxide-semiconductor transistor (CMOS) process with 4.5 x 2.5 mm(2) area. It operates at a rate of 1000 frames per second with 10 MHz chip main clock. The experiment results demonstrate that a high-speed target can be tracked in complex static background and a high-speed target among other high-speed objects can be tracked in clean background.

A base-emitter self-aligned multi-finger Si1-xGex/Si power heterojunction bipolar transistor

With a crystal orientation dependent on the etch rate of Si in KOH-based solution, a base-emitter self-aligned large-area multi-linger configuration power SiGe heterojunction bipolar transistor (HBT) device (with an emitter area of about 880 mu m(2)) is fabricated with 2 mu m double-mesa technology. The maximum dc current gain is 226.1. The collector-emitter junction breakdown voltage BVCEO is 10 V and the collector-base junction breakdown voltage BVCBO is 16 V with collector doping concentration of 1 x 10(17) cm(-3) and thickness of 400 nm. The device exhibited a maximum oscillation frequency f(max) of 35.5 GHz and a cut-off frequency f(T) of 24.9 GHz at a dc bias point of I-C = 70 mA and the voltage between collector and emitter is V-CE = 3 V. Load pull measurements in class-A operation of the SiGe HBT are performed at 1.9 GHz with input power ranging from 0 dBm to 21 dBm. A maximum output power of 29.9 dBm (about 977 mW) is obtained at an input power of 18.5 dBm with a gain of 11.47 dB. Compared to a non-self-aligned SiGe HBT with the same heterostructure and process, f(max) and f(T) are improved by about 83.9% and 38.3%, respectively.

Quantum measurement characteristics of a double-dot single electron transistor

Owing to a few unique advantages, the double-dot single electron transistor has been proposed as an alternative detector for charge states. In this work, we present a further study for its signal-to-noise property, based on a full analysis of the setup configuration symmetry. It is found that the effectiveness of the double-dot detector can approach that of an ideal detector, if the symmetric capacitive coupling is taken into account. The quantum measurement efficiency is also analyzed by comparing the measurement time with the measurement-induced dephasing time.

Silicon light emitting devices in CMOS technology

Two silicon light emitting devices with different structures are realized in standard 0.35 mu m complementary metal-oxide-semiconductor (CMOS) technology. They operate in reverse breakdown mode and can be turned on at 8.3 V. Output optical powers of 13.6 nW and 12.1 nW are measured at 10 V and 100 mA, respectively, and both the calculated light emission intensities are more than 1 mW/Cm-2. The optical spectra of the two devices are between 600-790 nm with a clear peak near 760 nm..

Correlation between optical and electrical properties in In0.52Al0.48As/InxGa1-xAs metamorphic high-electron-mobility-transistor structures on GaAs substrates

4.2 K photoluminescence (PL) and 77 K standard Hall-effect measurements were performed for In0.52Al0.48As/InxGa1-xAs metamorphic high-electron-mobility-transistor (HEMT) structures grown on GaAs substrates with different indium contents in the InxGa1-xAs well or different Si delta-doping concentrations. It was found that electron concentrations increased with increasing PL intensity ratio of the "forbidden" transition (the second electron subband to the first heavy-hole subband) to the sum of the "allowed" transition (the first electron subband to the first heavy-hole subband) and the forbidden transition. And electron mobilities decreased with increasing product of the average full width at half maximum of allowed and forbidden transitions and the electron effective mass in the InxGa1-xAs quantum well. These results show that PL measurements are a good supplemental tool to Hall-effect measurements in optimization of the HEMT layer structure. (c) 2006 American Institute of Physics.