Measurement of a Structured Backflow in an Open Small Channel Induced by Surface-Tension Gradients

We present experiments in which the laterally confined flow of a surfactant film driven by controlled surface tension gradients causes the subtended liquid layer to self-organize into an inner upstream microduct surrounded by the downstream flow. The anomalous interfacial flow profiles and the concomitant backflow are a result of the feedback between two-dimensional and three-dimensional microfluidics realized during flow in open microchannels. Bulk and surface particle image velocimetry data combined with an interfacial hydrodynamics model explain the dependence of the observed phenomena on channel geometry.

Amazon deforestation alters small stream structure, nitrogen biogeochemistry and connectivity to larger rivers

Human activities that modify land cover can alter the structure and biogeochemistry of small streams but these effects are poorly known over large regions of the humid tropics where rates of forest clearing are high. We examined how conversion of Amazon lowland tropical forest to cattle pasture influenced the physical and chemical structure, organic matter stocks and N cycling of small streams. We combined a regional ground survey of small streams with an intensive study of nutrient cycling using (15)N additions in three representative streams: a second-order forest stream, a second-order pasture stream and a third-order pasture stream. These three streams were within several km of each other and on similar soils. Replacement of forest with pasture decreased stream habitat complexity by changing streams from run and pool channels with forest leaf detritus (50% cover) to grass-filled (63% cover) channel with runs of slow-moving water. In the survey, pasture streams consistently had lower concentrations of dissolved oxygen and nitrate (NO(3) (-)) compared with similar-sized forest streams. Stable isotope additions revealed that second-order pasture stream had a shorter NH(4) (+) uptake length, higher uptake rates into organic matter components and a shorter (15)NH(4) (+) residence time than the second-order forest stream or the third-order pasture stream. Nitrification was significant in the forest stream (19% of the added (15)NH(4) (+)) but not in the second-order pasture (0%) or third-order (6%) pasture stream. The forest stream retained 7% of added (15)N in organic matter compartments and exported 53% ((15)NH(4) (+) = 34%; (15)NO(3) (-) = 19%). In contrast, the second-order pasture stream retained 75% of added (15)N, predominantly in grasses (69%) and exported only 4% as (15)NH(4) (+). The fate of tracer (15)N in the third-order pasture stream more closely resembled that in the forest stream, with 5% of added N retained and 26% exported ((15)NH(4) (+) = 9%; (15)NO(3) (-) = 6%). These findings indicate that the widespread infilling by grass in small streams in areas deforested for pasture greatly increases the retention of inorganic N in the first- and second-order streams, which make up roughly three-fourths of total stream channel length in Amazon basin watersheds. The importance of this phenomenon and its effect on N transport to larger rivers across the larger areas of the Amazon Basin will depend on better evaluation of both the extent and the scale at which stream infilling by grass occurs, but our analysis suggests the phenomenon is widespread.

Analysis of source-follower buffers implemented with graded-channel SOI nMOSFETs operating at cryogenic temperatures

This work studies the operation of source-follower buffers implemented with standard and graded-channel (GC) fully depleted (FD) SCI nMOSFETs at low temperatures. The analysis is performed by comparing the voltage gain of buffers implemented with GC and standard SOI nMOS transistors considering devices with the same mask channel length and same effective channel length. It is shown that the use of GC devices allows for achieving improved gain in all inversion levels in a wide range of temperatures. In addition, this improvement increases as temperature is reduced. It is shown that GC transistors can provide virtually constant gain, while for standard devices, the gain departs from the maximum value depending on the temperature and inversion level imposed by the bias current and input voltage. Two-dimensional numerical simulations were performed in order to study the reasons for the enhanced gain of GC MOSFETs at low temperatures. (C) 2009 Elsevier Ltd. All rights reserved.

Advantages of graded-channel SOI nMOSFETs for application as source-follower analog buffer

In this work the performance of graded-channel (CC) SOI MOSFETs operating as source-follower buffers is presented. The experimental analysis is performed by comparing the gain and linearity of buffers implemented with CC and standard SOI MOS devices considering the same mask dimensions. It is shown that by using CC devices, buffer gain very close to the theoretical limit can be achieved, with improved linearity, while for standard devices the gain departs from the theoretical value depending on the inversion level imposed by the bias current and input voltage. Two-dimensional numerical simulations were performed in order to confirm some hypotheses proposed to explain the gain behavior observed in the experimental data. By using numerical simulations the channel length has been varied, showing that the gain of buffers implemented with CC devices remains close to the theoretical limit even when short-channel devices are adopted. It has also been shown that the length of a source-follower buffer using CC devices can be reduced by a factor of 5, in comparison with a standard Sol MOSFET, without gain loss or linearity degradation. (C) 2008 Elsevier Ltd. All rights reserved.

Harmonic distortion analysis of double gate graded-channel MOSFETs operating in saturation

In this work we present an analysis of harmonic distortion (HD) in graded-channel (GC) gate-all-a round (GAA) devices operating in saturation region for analog applications. The study has been performed through device characterization and two-dimensional process and device simulations. The overall study has been done on the total and third order HDs. When applied in the saturation regime as an amplifier, the GC outperforms conventional GAA transistors presenting simultaneously higher transconductance, lower drain output conductance and more than 15 dB improved linearity. The influence of channel length reduction on the H D is also analyzed. Although slight linearity degradation is observed in both the conventional and the GC devices when reducing the channel length, the HD presented by the GC transistor is significantly lower than the one showed by conventional device for any Studied channel length. This allows AC input signal amplitude up to 20 times higher than the conventional GAA for a same specified distortion level. (C) 2008 Elsevier Ltd. All rights reserved.

Phototransistor with nanocrystalline Si/amorphous Si bilayer channel

We report a field-effect phototransistor with a channel comprising a thin nanocrystalline silicon transport layer and a thicker hydrogenated amorphous silicon absorption layer. The semiconductor and dielectric layers were deposited by radio-frequency plasma enhanced chemical vapor deposition. The phototransistor with channel length of 24 microns and photosensitive area of 1.4 mm(2) shows an off-current of about 1 pA, and high photoconductive gain in the subthreshold region. Measurements of the quantum efficiency at different incident light intensities and biasing conditions, along with spectral-response characteristics, and threshold voltage stability characterization demonstrate the feasibility of the phototransistor for low light level detection.

A III-V channel field effect transistor for non-classical CMOS: process optimisation for improved gate stack function

This thesis describes a collection of studies into the electrical response of a III-V MOS stack comprising metal/GaGdO/GaAs layers as a function of fabrication process variables and the findings of those studies. As a result of this work, areas of improvement in the gate process module of a III-V heterostructure MOSFET were identified. Compared to traditional bulk silicon MOSFET design, one featuring a III-V channel heterostructure with a high-dielectric-constant oxide as the gate insulator provides numerous benefits, for example: the insulator can be made thicker for the same capacitance, the operating voltage can be made lower for the same current output, and improved output characteristics can be achieved without reducing the channel length further. It is known that transistors composed of III-V materials are most susceptible to damage induced by radiation and plasma processing. These devices utilise sub-10 nm gate dielectric films, which are prone to contamination, degradation and damage. Therefore, throughout the course of this work, process damage and contamination issues, as well as various techniques to mitigate or prevent those have been investigated through comparative studies of III-V MOS capacitors and transistors comprising various forms of metal gates, various thicknesses of GaGdO dielectric, and a number of GaAs-based semiconductor layer structures. Transistors which were fabricated before this work commenced, showed problems with threshold voltage control. Specifically, MOSFETs designed for normally-off (VTH > 0) operation exhibited below-zero threshold voltages. With the results obtained during this work, it was possible to gain an understanding of why the transistor threshold voltage shifts as the gate length decreases and of what pulls the threshold voltage downwards preventing normally-off device operation. Two main culprits for the negative VTH shift were found. The first was radiation damage induced by the gate metal deposition process, which can be prevented by slowing down the deposition rate. The second was the layer of gold added on top of platinum in the gate metal stack which reduces the effective work function of the whole gate due to its electronegativity properties. Since the device was designed for a platinum-only gate, this could explain the below zero VTH. This could be prevented either by using a platinum-only gate, or by matching the layer structure design and the actual gate metal used for the future devices. Post-metallisation thermal anneal was shown to mitigate both these effects. However, if post-metallisation annealing is used, care should be taken to ensure it is performed before the ohmic contacts are formed as the thermal treatment was shown to degrade the source/drain contacts. In addition, the programme of studies this thesis describes, also found that if the gate contact is deposited before the source/drain contacts, it causes a shift in threshold voltage towards negative values as the gate length decreases, because the ohmic contact anneal process affects the properties of the underlying material differently depending on whether it is covered with the gate metal or not. In terms of surface contamination; this work found that it causes device-to-device parameter variation, and a plasma clean is therefore essential. This work also demonstrated that the parasitic capacitances in the system, namely the contact periphery dependent gate-ohmic capacitance, plays a significant role in the total gate capacitance. This is true to such an extent that reducing the distance between the gate and the source/drain ohmic contacts in the device would help with shifting the threshold voltages closely towards the designed values. The findings made available by the collection of experiments performed for this work have two major applications. Firstly, these findings provide useful data in the study of the possible phenomena taking place inside the metal/GaGdO/GaAs layers and interfaces as the result of chemical processes applied to it. In addition, these findings allow recommendations as to how to best approach fabrication of devices utilising these layers.

Threshold voltages of SOI MuGFETs

The multiple-gate field-effect transistor (MuGFET) is a device with a gate folded on different sides of the channel region. They are one of the most promising technological solutions to create high-performance ultra-scaled SOI CMOS. In this work, the behavior of the threshold voltage in double-gate, triple-gate and quadruple-gate SOI transistors with different channel doping concentrations is studied through three-dimensional numerical simulation. The results indicated that for double-gate transistors, one or two threshold voltages can be observed, depending on the channel doping concentration. However, in triple-gate and quadruple-gate it is possible to observe up to four threshold voltages due to the corner effect and the different doping concentration between the top and bottom of the Fin. (C) 2008 Elsevier Ltd. All rights reserved.

Analog performance of standard and strained triple-gate silicon-on-insulator nFinFETs

This work shows a comparison between the analog performance of standard and strained Si n-type triple-gate FinFETs with high-K dielectrics and TiN gate material. Different channel lengths and fin widths are studied. It is demonstrated that both standard and strained FinFETs with short channel length and narrow fins have similar analog properties, whereas the increase of the channel length degrades the early voltage of the strained devices, consequently decreasing the device intrinsic voltage gain with respect to standard ones. Narrow strained FinFETs with long channel show a degradation of the Early voltage if compared to standard ones suggesting that strained devices are more subjected to the channel length modulation effect. (C) 2008 Elsevier Ltd. All rights reserved.

Improved generation lifetime model for the electrical characterization of single- and double-gate SOI nMOSFETs

This work proposes a refined technique for the extraction of the generation lifetime in single- and double-gate partially depleted SOI nMOSFETs. The model presented in this paper, based on the drain current switch-off transients, takes into account the influence of the laterally non-uniform channel doping, caused by the presence of the halo implanted region, and the amount of charge controlled by the drain and source junctions on the floating body effect when the channel length is reduced. The obtained results for single- gate (SG) devices are compared with two-dimensional numerical simulations and experimental data, extracted for devices fabricated in a 0.1 mu m SOI CMOS technology, showing excellent agreement. The improved model to determine the generation lifetime in double-gate (DG) devices beyond the considerations previously presented also consider the influence of the silicon layer thickness on the drain current transient. The extracted data through the improved model for DG devices were compared with measurements and two-dimensional numerical simulations of the SG devices also presenting a good adjustment with the channel length reduction and the same tendency with the silicon layer thickness variation.

Impact of SEG on uniaxially strained MuGFET performance

This work focuses on the impact of the source and drain Selective Epitaxial Growth (SEG) on the performance of uniaxially strained MuGFETs. With the channel length reduction, the normalized transconductance (gm.L./W) of unstressed MuGFETs decreases due to the series resistance and short channel effects (SCE), while the presence of uniaxial strain improves the gm. The competition between the series resistance (R(s)) and the uniaxial strain results in a normalized gm maximum point for a specific channel length. Since the SEG structure influences both R(s) and the strain in the channel, this work studies from room down to low temperature how these effects influence the performance of the triple-gate FETs. For lower temperatures, the strain-induced mobility enhancement increases and leads to a shift in the maximum point towards shorter channel lengths for devices without SEG. This shift is not observed for devices with SEG where the strain level is much lower. At 150 K the gm behavior of short channel strained devices with SEG is similar to the non SEC ones due to the better gm temperature enhancement for devices without SEG caused by the strain. For lower temperatures SEG structure is not useful anymore. (C) 2011 Elsevier Ltd. All rights reserved.

Evidence of multiple transcription initiation and termination sites within the rDNA intergenic spacer and rRNA readthrough transcription in the urochordate Herdmania curvata

Analysis of the structure of the urochordate Herdmania curvata ribosomal DNA intergenic spacer (IGS) and its role in transcription initiation and termination suggests that rRNA gene regulation in this chordate differs from that in vertebrates. A cloned H, curvata IGS is 1881 bp and composed predominantly of two classes of similar repeat sequences that largely alternate in a tandem array. Southern blot hybridization demonstrates that the IGS length variation within an individual and population is largely the result of changes in internal repeat number. Nuclease S1 mapping and primer extension analyses suggest that there are two transcription initiation sites at the 3' end of the most 3' repetitive element; these sites are 6 nucleotides apart. Unlike mouse, Xenopus, and Drosophila, there is no evidence of transcription starting elsewhere in the IGS. Most sequence differences between the promoter repeat and the other internal repeats are in the vicinity of the putative initiation sites. As in Drosophila, nuclease S1 mapping of transcription termination sites suggest that there is not a definitive stop site and a majority of the pre-rRNAs read through a substantial portion of the IGS. Some transcription appears to proceed completely through the promoter repeat into the adjacent rDNA unit. Analysis of oocyte RNA by reverse transcription-polymerase chain reaction (RT-PCR) confirms that readthrough transcription into the adjacent rDNA unit is occurring in some small IGS length variants; there is no evidence of complete readthrough of IGSs larger than 1.0 kb.

Metodologia para obtenção do hidrograma de escoamento superficial em encostas e canais. Parte II: modelo computacional e análise de sensibilidade

Estimativas de vazão máxima de escoamento superficial são necessárias para o projeto de obras hidráulicas em bacias urbanas e rurais. A dificuldade em aplicar os procedimentos disponíveis para calcular a variação do escoamento superficial com o tempo e de seu valor máximo deve-se à inexatidão dos métodos usados para esse objetivo e à variabilidade nos resultados que podem ser obtidos por profissionais que usem o mesmo procedimento. Dessa forma, a investigação de um método que produza estimativas confiáveis da vazão máxima e do hidrograma de escoamento superficial é de grande interesse. Neste trabalho, desenvolveu-se e avaliou-se a sensibilidade de um software (HIDROGRAMA 2.1) que permite a obtenção do hidrograma de escoamento superficial, da vazão máxima e seu tempo de ocorrência, da altura e da velocidade máximas do escoamento, do volume e da lâmina de escoamento superficial em encosta e em canais. O modelo apresentou grande sensibilidade ao período de retorno, à taxa de infiltração estável e ao comprimento da encosta e do canal.