Effects of Parasitics and Interface Traps on Ballistic Nanowire FET in the Ultimate Quantum Capacitance Limit

In this paper, we focus on the performance of a nanowire field-effect transistor in the ultimate quantum capacitance limit (UQCL) (where only one subband is occupied) in the presence of interface traps (D-it), parasitic capacitance (C-L), and source/drain series resistance (R-s,R-d), using a ballistic transport model and compare the performance with its classical capacitance limit (CCL) counterpart. We discuss four different aspects relevant to the present scenario, namely: 1) gate capacitance; 2) drain-current saturation; 3) subthreshold slope; and 4) scaling performance. To gain physical insights into these effects, we also develop a set of semianalytical equations. The key observations are as follows: 1) A strongly energy-quantized nanowire shows nonmonotonic multiple-peak C-V characteristics due to discrete contributions from individual subbands; 2) the ballistic drain current saturates better in the UQCL than in the CCL, both in the presence and absence of D-it and R-s,R-d; 3) the subthreshold slope does not suffer any relative degradation in the UQCL compared to the CCL, even with Dit and R-s,R-d; 4) the UQCL scaling outperforms the CCL in the ideal condition; and 5) the UQCL scaling is more immune to R-s,R-d, but the presence of D-it and C-L significantly degrades the scaling advantages in the UQCL.

Characterization of parasitics from scattering parameters of laser diode

A novel method for characterizing the parasitics of parasitic network is proposed based on the relations between the scattering parameters of a semiconductor laser chip and laser diode. Experiments are designed and performed using our method. The analysis results are in good agreement with the measurements. Furthermore, how the parasitics change with the parasitic element values are investigated. The method only needs reflection coefficient of laser diode to be measured, which is simple because of the developed electrical-domain measurement techniques. 2007 Wiley Periodicals, Inc.

Methods for characterization of packaging parasitics of semiconductor lasers

Two novel methods for analyzing the parasitics of packaging networks are proposed based on the relations between the scattering parameters of a semiconductor laser before and after packaging, and the experiments are designed and performed using our methods. It is found that the analysis results of the two methods are in good agreement with the measurements. Either of the two methods can provide an alternative approach for characterizing the packaging parasitics for semiconductor lasers, and both are convenient due to the developed measurement techniques. (c) 2005 Wiley Periodicals, Inc.

Characterization of parasitics in TO-packaged high-speed laser modules

An elaborate analysis of the parasitic network of high-speed through-hole packaging (TO)-type laser modules is presented using a small-signal equivalent circuit model. The intrinsic laser diode is obtained using the optical modulation technique, and is embedded into the model as a separate component. Three step-by-step measurements are made for determining the packaging parasitic network, including the test fixture, TO header, submount, bonding wire, and parasitics of the laser chip. A good agreement between simulated and measured results confirms the validation and accuracy of the characterization procedures. Furthermore, several key parasitic elements are found based on the simulation of the high-frequency responses of the packaged devices. It is expected that the 3-dB bandwidth of 12 GHz or more of the low-cost TO packaged laser module may be achieved using the proposed optimization method.

Bonding-wire compensation effect on the packaging parasitics of optoelectronic devices

The effect of bonding-wire compensation on the capacitances of both the submount and the laser diode is demonstrated in this paper. The measured results show that the small-signal magnitude-frequency responses of the TO packaged laser and photodiode modules can be improved by properly choosing the length of the bonding wire. After packaging, the phase-frequency responses of the laser modules can also be significantly improved (c) 2005 Wiley Periodicals, Inc.

The effect of circuit parasitics on resonant switched capacitor converters

Switched Capacitor (SC) converters have been used for several years in low-power, power electronic energy conversion systems. However, because of their attractive features such as low-weight and high-density energy conversion and with the emergence of new circuit topologies and SiC switching devices, these circuits have recently been proposed for higher power applications. The resonant switched capacitor topology is a good candidate for high-power due to its very low-switching loss, but circuit parasitic inductance and resistance can have a significant effect on the resonant frequency of each cell. This paper discusses the influence of these parasitics on the performance of the converter and proposes a method by which these parasitics can be estimated. Simulation results and measurements from a hardware prototype are used to validate the technique.

Microelectromechanical torsional varactors with low parasitic capacitances and high dynamic range

This work focuses on the design of torsional microelectromechanical systems (MEMS) varactors to achieve highdynamic range of capacitances. MEMS varactors fabricated through the polyMUMPS process are characterized at low and high frequencies for their capacitance-voltage characteristics and electrical parasitics. The effect of parasitic capacitances on tuning ratio is studied and an equivalent circuit is developed. Two variants of torsional varactors that help to improve the dynamic range of torsional varactors despite the parasitics are proposed and characterized. A tuning ratio of 1:8, which is the highest reported in literature, has been obtained. We also demonstrate through simulations that much higher tuning ratios can be obtained with the designs proposed. The designs and experimental results presented are relevant to CMOS fabrication processes that use low resistivity substrate. (C) 2012 Society of Photo-Optical Instrumentation Engineers (SPIE). DOI: 10.1117/1.JMM.11.1.013006]

Electronically tunable zero order resonator based on CRLH-TLs

Composite Right/Left Handed (CRLH) transmission line (TL) based electronically tunable 1.5 cell zero order resonator (ZOR) is demonstrated with microstrip technology by use of varactors. A novel mechanism for DC bias for the varactor is proposed. This is achieved by patterning the ground plane of microstrip thereby reducing the complexity of DC feed mechanism. This approach also mitigates the effect of parasitics arising from DC feed choke appearing in the RF signal path.

Methods for enhanced electrical transduction and characterization of micromechanical resonators

This paper details the design and enhanced electrical transduction of a bulk acoustic mode resonator fabricated in a commercial foundry MEMS process utilizing 2.5 μm gaps. The I-V characteristics of electrically addressed silicon resonators are often dominated by capacitive parasitics, inherent to hybrid technologies. This paper benchmarks a variety of drive and detection principles for electrostatically driven square-extensional mode resonators operating in air via analytical models accompanied by measurements of fabricated devices with the primary aim of enhancing the ratio of the motional to feedthrough current at nominal operating voltages. In view of ultimately enhancing the motional to feedthrough current ratio, a new detection technique that combines second harmonic capacitive actuation and piezoresistive detection is presented herein. This new method is shown to outperform previously reported methods utilizing voltages as low as ±3 V in air, providing a promising solution for low voltage CMOS-MEMS integration. To elucidate the basis of this improvement in signal output from measured devices, an approximate analytical model for piezoresistive sensing specific to the resonator topology reported here is also developed and presented. © 2010 Elsevier B.V. All rights reserved.

Device and circuit-level performance of carbon nanotube field-effect transistor with benchmarking against a nano-MOSFET

The performance of a semiconducting carbon nanotube (CNT) is assessed and tabulated for parameters against those of a metal-oxide-semiconductor field-effect transistor (MOSFET). Both CNT and MOSFET models considered agree well with the trends in the available experimental data. The results obtained show that nanotubes can significantly reduce the drain-induced barrier lowering effect and subthreshold swing in silicon channel replacement while sustaining smaller channel area at higher current density. Performance metrics of both devices such as current drive strength, current on-off ratio (Ion/Ioff), energy-delay product, and power-delay product for logic gates, namely NAND and NOR, are presented. Design rules used for carbon nanotube field-effect transistors (CNTFETs) are compatible with the 45-nm MOSFET technology. The parasitics associated with interconnects are also incorporated in the model. Interconnects can affect the propagation delay in a CNTFET. Smaller length interconnects result in higher cutoff frequency. © 2012 Tan et al.

Dead-time minimisation using active voltage control gate drive for high-power IGBT converters

High-power converters usually need longer dead-times than their lower-power counterparts and a lower switching frequency. Also due to the complicated assembly layout and severe variations in parasitics, in practice the conventional dead-time specific adjustment or compensation for high-power converters is less effective, and usually this process is time-consuming and bespoke. For general applications, minimising or eliminating dead-time in the gate drive technology is a desirable solution. With the growing acceptance of power electronics building blocks (PEBB) and intelligent power modules (IPM), gate drives with intelligent functions are in demand. Smart functions including dead time elimination/minimisation can improve modularity, flexibility and reliability. In this paper, a dead-time minimisation using Active Voltage Control (AVC) gate drive is presented. © 2012 IEEE.

Overall optimization of high-speed semiconductor laser modules

Based on the high frequency techniques such as frequency response measurement, equivalent circuit modeling and packaging parasitics compensation, a comprehensive optimization method for packaging high-speed semiconductor laser module is presented in this paper. The experiments show that the small-signal magnitude frequency response of the TO packaged laser module is superior to that of laser diode in frequencies, and the in-band flatness and the phase-frequency linearity are also improved significantly.

Subtraction of scattering parameters for small-signal modulation characteristics of laser diode

An extended subtraction method of scattering parameters for characterizing laser diode is proposed in this paper. The intrinsic response is extracted from the measured transmission coefficients of laser diode, and the parasitics of packaging net-work laser chip are determined from the measured reflection coefficient of laser diode simultaneously. It is shown that the theories agree well with the experimental results.

A 16-term error model based on linear equations of voltage and current variables

Formulation of a 16-term error model, based on the four-port ABCD-matrix and voltage and current variables, is outlined. Matrices A, B, C, and D are each 2 x 2 submatrices of the complete 4 x 4 error matrix. The corresponding equations are linear in terms of the error parameters, which simplifies the calibration process. The parallelism with the network analyzer calibration procedures and the requirement of five two-port calibration measurements are stressed. Principles for robust choice of equations are presented. While the formulation is suitable for any network analyzer measurement, it is expected to be a useful alternative for the nonlinear y-parameter approach used in intrinsic semiconductor electrical and noise parameter measurements and parasitics' deembedding.