Differential mixer with NMOS/PMOS stack at switching stage

This paper proposes a novel differential mixer topology. The traditional stage of switching is replaced by a stack of NMOS and PMOS transistors combined. A design is given of a 900 MHz down-conversion mixer using a 0.35 μm CMOS process. Comparison with conventional mixer shows that the topology leads to a better performance in terms of conversion gain and linearity. ©2012 IEEE.

Using pMOS Pass-Gates to Boost SRAM Performance by Exploiting Strain Effects in Sub-20-nm FinFET Technologies

Strained fin is one of the techniques used to improve the devices as their size keeps reducing in new nanoscale nodes. In this paper, we use a predictive technology of 14 nm where pMOS mobility is significantly improved when those devices are built on top of long, uncut fins, while nMOS devices present the opposite behavior due to the combination of strains. We explore the possibility of boosting circuit performance in repetitive structures where long uncut fins can be exploited to increase fin strain impact. In particular, pMOS pass-gates are used in 6T complementary SRAM cells (CSRAM) with reinforced pull-ups. Those cells are simulated under process variability and compared to the regular SRAM. We show that when layout dependent effects are considered the CSRAM design provides 10% to 40% faster access time while keeping the same area, power, and stability than a regular 6T SRAM cell. The conclusions also apply to 8T SRAM cells. The CSRAM cell also presents increased reliability in technologies whose nMOS devices have more mismatch than pMOS transistors.

Photolithography based patterning of bacteriorhodopsin films

The patterning of photoactive purple membrane (PM) films onto electronic substrates to create a biologically based light detection device was investigated. This research is part of a larger collaborative effort to develop a miniaturized toxin detection platform. This platform will utilize PM films containing the photoactive protein bacteriorhodopsin to convert light energy to electrical energy. Following an effort to pattern PM films using focused ion beam machining, the photolithography based bacteriorhodopsin patterning technique (PBBPT) was developed. This technique utilizes conventional photolithography techniques to pattern oriented PM films onto flat substrates. After the basic patterning process was developed, studies were conducted that confirmed the photoelectric functionality of the PM films after patterning. Several process variables were studied and optimized in order to increase the pattern quality of the PM films. Optical microscopy, scanning electron microscopy, and interferometric microscopy were used to evaluate the PM films produced by the patterning technique. Patterned PM films with lateral dimensions of 15 μm have been demonstrated using this technique. Unlike other patterning techniques, the PBBPT uses standard photolithographic processes that make its integration with conventional semiconductor fabrication feasible. The final effort of this research involved integrating PM films patterned using the PBBPT with PMOS transistors. An indirect integration of PM films with PMOS transistors was successfully demonstrated. This indirect integration used the voltage produced by a patterned PM film under light exposure to modulate the gate of a PMOS transistor, activating the transistor. Following this success, a study investigating how this PM based light detection system responded to variations in light intensity supplied to the PM film. This work provides a successful proof of concept for a portion of the toxin detection platform currently under development.

Low subthreshold slope in junctionless multigate transistors

The improvement of subthreshold slope due to impact ionization is compared between ""standard"" inversion-mode multigate silicon nanowire transistors and junctionless transistors. The length of the region over which impact ionization takes place, as well as the amplitude of the impact ionization rate are found to be larger in the junctionless devices, which reduces the drain voltage necessary to obtain a sharp subthreshold slope. (C) 2010 American Institute of Physics. [doi: 10.1063/1.3358131]

Cryogenic Operation of Junctionless Nanowire Transistors

This letter presents the properties of nMOS junctionless nanowire transistors (JNTs) under cryogenic operation. Experimental results of drain current, subthreshold slope, maximum transconductance at low electric field, and threshold voltage, as well as its variation with temperature, are presented. Unlike in classical devices, the drain current of JNTs decreases when temperature is lowered, although the maximum transconductance increases when the temperature is lowered down to 125 K. An analytical model for the threshold voltage is proposed to explain the influence of nanowire width and doping concentration on its variation with temperature. It is shown that the wider the nanowire or the lower the doping concentration, the higher the threshold voltage variation with temperature.

Junctionless Multiple-Gate Transistors for Analog Applications

This paper presents the evaluation of the analog properties of nMOS junctionless (JL) multigate transistors, comparing their performance with those exhibited by inversion-mode (IM) trigate devices of similar dimensions. The study has been performed for devices operating in saturation as single-transistor amplifiers, and we have considered the dependence of the analog properties on fin width W(fin) and temperature T. Furthermore, this paper aims at providing a physical insight into the analog parameters of JL transistors. For that, in addition to device characterization, 3-D device simulations were performed. It is shown that, depending on gate voltage, JL devices can present both larger Early voltage V(EA) and larger intrinsic voltage gain A(V) than IM devices of similar dimensions. In addition, V(EA) and A(V) are always improved in JL devices when the temperature is increased, whereas they present a maximum value around room temperature for IM transistors.

Single-spin measurement using single-electron transistors to probe two-electron systems

We present a method for measuring single spins embedded in a solid by probing two-electron systems with a single-electron transistor (SET). Restrictions imposed by the Pauli principle on allowed two-electron states mean that the spin state of such systems has a profound impact on the orbital states (positions) of the electrons, a parameter which SET's are extremely well suited to measure. We focus on a particular system capable of being fabricated with current technology: a Te double donor in Si adjacent to a Si/SiO2, interface and lying directly beneath the SET island electrode, and we outline a measurement strategy capable of resolving single-electron and nuclear spins in this system. We discuss the limitations of the measurement imposed by spin scattering arising from fluctuations emanating from the SET and from lattice phonons. We conclude that measurement of single spins, a necessary requirement for several proposed quantum computer architectures, is feasible in Si using this strategy.

Electric-field-induced Mott insulating states in organic field-effect transistors

We consider the possibility that the electrons injected into organic field-effect transistors are strongly correlated. A single layer of acenes can be modeled by a Hubbard Hamiltonian similar to that used for the κ-(BEDT-TTF)2X family of organic superconductors. The injected electrons do not necessarily undergo a transition to a Mott insulator state as they would in bulk crystals when the system is half-filled. We calculate the fillings needed for obtaining insulating states in the framework of the slave-boson theory and in the limit of large Hubbard repulsion U. We also suggest that these Mott states are unstable above some critical interlayer coupling or long-range Coulomb interaction.

A Step-up mu-Power Converter for Solar Energy Harvesting Applications, using Hill Climbing Maximum Power Point Tracking

This paper presents a step-up micro-power converter for solar energy harvesting applications. The circuit uses a SC voltage tripler architecture, controlled by an MPPT circuit based on the Hill Climbing algorithm. This circuit was designed in a 0.13 mu m CMOS technology in order to work with an a-Si PV cell. The circuit has a local power supply voltage, created using a scaled down SC voltage tripler, controlled by the same MPPT circuit, to make the circuit robust to load and illumination variations. The SC circuits use a combination of PMOS and NMOS transistors to reduce the occupied area. A charge re-use scheme is used to compensate the large parasitic capacitors associated to the MOS transistors. The simulation results show that the circuit can deliver a power of 1266 mu W to the load using 1712 mu W of power from the PV cell, corresponding to an efficiency as high as 73.91%. The simulations also show that the circuit is capable of starting up with only 19% of the maximum illumination level.

High-performance flexible hybrid field-effect transistors based on cellulose fiber paper

IEEE Electron Device Letters, VOL. 29, NO. 9,

Transparent oxide thin-film transistors: production, characterization and integration

In partial fulfillment of the requirements for the degree of Doctor of Philosophy in Nanotechnologies and Nanosciences by Universidade Nova de Lisboa Faculdade de Ciências e Tecnologia

Development of copper and nickel based oxide thin-films: design and fabrication of thin-film transistors

Dissertação para obtenção do Grau de Doutor em Nanotecnologia e Nanociência

Towards printed carbon nanotube transistors on paper substrates

This thesis reports the work performed in the optimization of deposition parameters of Multi – Walled Carbon Nanotubes (MWCNT) targeting the development of a Field Effect Transistors (FET) on paper substrates. The CNTs were dispersed in a water solution with sodium dodecyl sulphate (SDS) through ultrasonication, ultrasonic bath and a centrifugation to remove the supernatant and have a homogeneous solution. Several deposition tests were performed using different types of CNTs, dis-persants, papers substrates and deposition techniques, such as spray coating and inkjet printing. The characterization of CNTs was made by Scanning Electron Microscopy (SEM) and Hall Effect. The most suitable CNT coatings able to be used as semiconductor in FETs were deposited by spray coat-ing on a paper substrate with hydrophilic nanoporous surface (FS2) at 100 ºC, 4 bar, 10 cm height, 5 second of deposition time and 90 seconds of drying between steps (4 layers of CNTs were deposited). Planar electrolyte gated FETs were produced with these layers using gold-nickel gate, source and drain electrodes. Despite the small current modulation (Ion/Ioff ratio of 1.8) one of these devices have p-type conduction with a field effect mobility of 1.07 cm2/V.s.