Cryogenic Operation of Junctionless Nanowire Transistors

This letter presents the properties of nMOS junctionless nanowire transistors (JNTs) under cryogenic operation. Experimental results of drain current, subthreshold slope, maximum transconductance at low electric field, and threshold voltage, as well as its variation with temperature, are presented. Unlike in classical devices, the drain current of JNTs decreases when temperature is lowered, although the maximum transconductance increases when the temperature is lowered down to 125 K. An analytical model for the threshold voltage is proposed to explain the influence of nanowire width and doping concentration on its variation with temperature. It is shown that the wider the nanowire or the lower the doping concentration, the higher the threshold voltage variation with temperature.

Modeling multiple state electrostatically formed nanowire transistors

The present thesis work proposes a new physical equivalent circuit model for a recently proposed semiconductor transistor, a 2-drain MSET (Multiple State Electrostatically Formed Nanowire Transistor). It presents a new software-based experimental setup that has been developed for carrying out numerical simulations on the device and on equivalent circuits. As of 2015, we have already approached the scaling limits of the ubiquitous CMOS technology that has been in the forefront of mainstream technological advancement, so many researchers are exploring different ideas in the realm of electrical devices for logical applications, among them MSET transistors. The idea that underlies MSETs is that a single multiple-terminal device could replace many traditional transistors. In particular a 2-drain MSET is akin to a silicon multiplexer, consisting in a Junction FET with independent gates, but with a split drain, so that a voltage-controlled conductive path can connect either of the drains to the source. The first chapter of this work presents the theory of classical JFETs and its common equivalent circuit models. The physical model and its derivation are presented, the current state of equivalent circuits for the JFET is discussed. A physical model of a JFET with two independent gates has been developed, deriving it from previous results, and is presented at the end of the chapter. A review of the characteristics of MSET device is shown in chapter 2. In this chapter, the proposed physical model and its formulation are presented. A listing for the SPICE model was attached as an appendix at the end of this document. Chapter 3 concerns the results of the numerical simulations on the device. At first the research for a suitable geometry is discussed and then comparisons between results from finite-elements simulations and equivalent circuit runs are made. Where points of challenging divergence were found between the two numerical results, the relevant physical processes are discussed. In the fourth chapter the experimental setup is discussed. The GUI-based environments that allow to explore the four-dimensional solution space and to analyze the physical variables inside the device are described. It is shown how this software project has been structured to overcome technical challenges in structuring multiple simulations in sequence, and to provide for a flexible platform for future research in the field.

Universal zero-bias conductance for the single-electron transistor

The thermal dependence of the zero-bias conductance for the single electron transistor is the target of two independent renormalization-group approaches, both based on the spin-degenerate Anderson impurity model. The first approach, an analytical derivation, maps the Kondo-regime conductance onto the universal conductance function for the particle-hole symmetric model. Linear, the mapping is parametrized by the Kondo temperature and the charge in the Kondo cloud. The second approach, a numerical renormalization-group computation of the conductance as a function the temperature and applied gate voltages offers a comprehensive view of zero-bias charge transport through the device. The first approach is exact in the Kondo regime; the second, essentially exact throughout the parametric space of the model. For illustrative purposes, conductance curves resulting from the two approaches are compared.

Transmit array of transistor amplifiers illuminated by a patch array in the reactive near-field region

In this paper, a small transmit array of transistor amplifiers illuminated by a passive array of microstrip patches in the reactive near-field region is investigated as a power-combining structure. The two cases considered are when the transmit array radiates in a free space and when a passive array similar to the one used for illumination collects the radiated power. A comparison of the performance of the proposed structure against the alternative one, which uses a conventional horn antenna as a power-launching/receiving device, is also presented.

Facile synthesis of freestanding Si nanowire arrays by one-step template-free electro-deoxidation of SiO2 in molten salt

This communication presents a novel kind of silicon nanomaterial: freestanding Si nanowire arrays (Si NWAs), which are synthesized facilely by one-step template-free electro-deoxidation of SiO2 in molten CaCl2. The self-assembling growth process of this material is also investigated preliminarily.

Fully transparent ZnO thin-film transistor produced at room temperature

Advanced Materials, Vol. 17, nº 5

Write-erase and read paper memory transistor

Applied Physics Letters, Vol.93, issue 20

Development of paper transistor with memory effect

This work will discuss the use of different paper membranes as both the substrate and dielectric for field-effect memory transistors. Three different nanofibrillated cellulose membranes (NFC) were used as the dielectric layer of the memory transistors (NFC), one with no additives, one with an added polymer PAE and one with added HCl. Gallium indium zinc oxide (GIZO) was used as the device’s semiconductor and gallium aluminium zinc oxide (GAZO) was used as the gate electrode. Fourier transform infrared spectroscopy (FTIR) was used to access the water content of the paper membranes before and after vacuum. It was found that the devices recovered their water too quickly for a difference to be noticeable in FTIR. The transistor’s electrical performance tests yielded a maximum ION/IOFF ratio of around 3,52x105 and a maximum subthreshold swing of 0,804 V/decade. The retention time of the dielectric charge that grants the transistor its memory capabilities was accessed by the measurement of the drain current periodically during 144 days. During this period the mean drain current did not lower, leaving the retention time of the device indeterminate. These results were compared with similar devices revealing these devices to be at the top tier of the state-of-the-art.

Silicon nanowire arrays coupled with cobalt phosphide spheres as low-cost photocathodes for efficient solar hydrogen evolution

We demonstrate the first example of silicon nanowire array photocathodes coupled with hollow spheres of the emerging earth-abundant cobalt phosphide catalysts. Compared to bare silicon nanowire arrays, the hybrid electrodes exhibit significantly improved photoelectrochemical performance toward the solar-driven H2 evolution reaction.

Simulations of parasitic and intrinsic capacitances related to Multiple-Gate-Field-Effect Transistor architectures

Report for the scientific sojourn carried out at the Université Catholique de Louvain, Belgium, from March until June 2007. In the first part, the impact of important geometrical parameters such as source and drain thickness, fin spacing, spacer width, etc. on the parasitic fringing capacitance component of multiple-gate field-effect transistors (MuGFET) is deeply analyzed using finite element simulations. Several architectures such as single gate, FinFETs (double gate), triple-gate represented by Pi-gate MOSFETs are simulated and compared in terms of channel and fringing capacitances for the same occupied die area. Simulations highlight the great impact of diminishing the spacing between fins for MuGFETs and the trade-off between the reduction of parasitic source and drain resistances and the increase of fringing capacitances when Selective Epitaxial Growth (SEG) technology is introduced. The impact of these technological solutions on the transistor cut-off frequencies is also discussed. The second part deals with the study of the effect of the volume inversion (VI) on the capacitances of undoped Double-Gate (DG) MOSFETs. For that purpose, we present simulation results for the capacitances of undoped DG MOSFETs using an explicit and analytical compact model. It monstrates that the transition from volume inversion regime to dual gate behaviour is well simulated. The model shows an accurate dependence on the silicon layer thickness,consistent withtwo dimensional numerical simulations, for both thin and thick silicon films. Whereas the current drive and transconductance are enhanced in volume inversion regime, our results show thatintrinsic capacitances present higher values as well, which may limit the high speed (delay time) behaviour of DG MOSFETs under volume inversion regime.

Via-configurable transistor array: a regular design technique to improve ICs yield

Process variations are a major bottleneck for digital CMOS integrated circuits manufacturability and yield. That iswhy regular techniques with different degrees of regularity are emerging as possible solutions. Our proposal is a new regular layout design technique called Via-Configurable Transistors Array (VCTA) that pushes to the limit circuit layout regularity for devices and interconnects in order to maximize regularity benefits. VCTA is predicted to perform worse than the Standard Cell approach designs for a certain technology node but it will allow the use of a future technology on an earlier time. Ourobjective is to optimize VCTA for it to be comparable to the Standard Cell design in an older technology. Simulations for the first unoptimized version of our VCTA of delay and energy consumption for a Full Adder circuit in the 90 nm technology node are presented and also the extrapolation for Carry-RippleAdders from 4 bits to 64 bits.

Structural and optical properties of high quality zinc-blende/wurtzite GaAs nanowire heterostructures

The structural and optical properties of three different kinds of GaAs nanowires with 100% zinc-blende structure and with an average of 30% and 70% wurtzite are presented. A variety of shorter and longer segments of zinc-blende or wurtzite crystal phases are observed by transmission electron microscopy in the nanowires. Sharp photoluminescence lines are observed with emission energies tuned from 1.515 eV down to 1.43 eV when the percentage of wurtzite is increased. The downward shift of the emission peaks can be understood by carrier confinement at the interfaces, in quantum wells and in random short period superlattices existent in these nanowires, assuming a staggered band offset between wurtzite and zinc-blende GaAs. The latter is confirmed also by time-resolved measurements. The extremely local nature of these optical transitions is evidenced also by cathodoluminescence measurements. Raman spectroscopy on single wires shows different strain conditions, depending on the wurtzite content which affects also the band alignments. Finally, the occurrence of the two crystallographic phases is discussed in thermodynamic terms.

Optical and electrical properties of amorphous zinc tin oxide thin films examined for thin film transistor application

Structural, electronic, and optical properties of amorphous and transparent zinc tin oxide films deposited on glass substrates by pulsed laser deposition (PLD) were examined for two chemical compositions of Zn:Sn=1:1 and 2:1 as a function of oxygen partial pressure PO2 used for the film deposition and annealing temperature. Different from a previous report on sputter-deposited films Chiang et al., Appl. Phys. Lett. 86, 013503 2005 , the PLD-deposited films crystallized at a lower temperature 450 °C to give crystalline ZnO and SnO2 phases. The optical band gaps Tauc gaps were 2.80−2.85 eV and almost independent of oxygen PO2 , which are smaller than those of the corresponding crystals 3.35−3.89 eV . Films deposited at low PO2 showed significant subgap absorptions, which were reduced by postthermal annealing. Hall mobility showed steep increases when carrier concentration exceeded threshold values and the threshold value depended on the film chemical composition. The films deposited at low PO2 2 Pa had low carrier concentrations. It is thought that the low PO2 produced high-density oxygen deficiencies and generated electrons, but these electrons were trapped in localized states, which would be observed as the subgap absorptions. Similar effects were observed for 600 °C crystallized films and their resistivities were increased by formation of subgap states due to the reducing high-temperature condition. High carrier concentrations and large mobilities were obtained in an intermediate PO2 region for the as-deposited films.

Development of p-type transparent semiconducting oxides for thin film transistor applications

Semiconductor physics has developed significantly in the field of re- search and industry in the past few decades due to it’s numerous practical applications. One of the relevant fields of current interest in material science is the fundamental aspects and applications of semi- conducting transparent thin films. Transparent conductors show the properties of transparency and conductivity simultaneously. As far as the band structure is concerned, the combination of the these two properties in the same material is contradictory. Generally a trans- parent material is an insulator having completely filled valence and empty conduction bands. Metallic conductivity come out when the Fermi level lies within a band with a large density of states to provide high carrier concentration. Effective transparent conductors must nec- essarily represent a compromise between a better transmission within the visible spectral range and a controlled but useful electrical con- ductivity [1–6]. Generally oxides like In2O3, SnO2, ZnO, CdO etc, show such a combination. These materials without any doping are insulators with optical band gap of about 3 eV. To become a trans- parent conductor, these materials must be degenerately doped to lift the Fermi level up into the conduction band. Degenerate doping pro- vides high mobility of extra carriers and low optical absorption. The increase in conductivity involves an increase in either carrier concen- tration or mobility. Increase in carrier concentration will enhance the absorption in the visible region while increase in mobility has no re- verse effect on optical properties. Therefore the focus of research for new transparent conducting oxide (TCO) materials is on developing materials with higher carrier mobilities.

El transistor como caja negra.

Estudio sobre el funcionamiento del transistor basándose en el aspecto utilitario o externo, tratando el transistor como una caja opaca, es decir, sin abrirlo y sin estudiar sus componentes internos, sino a través de ecuaciones físicas.