Self-consistent theory of current and voltage noise in multimode ballistic conductors

Electron transport in a self-consistent potential along a ballistic two-terminal conductor has been investigated. We have derived general formulas which describe the nonlinear current-voltage characteristics, differential conductance, and low-frequency current and voltage noise assuming an arbitrary distribution function and correlation properties of injected electrons. The analytical results have been obtained for a wide range of biases: from equilibrium to high values beyond the linear-response regime. The particular case of a three-dimensional Fermi-Dirac injection has been analyzed. We show that the Coulomb correlations are manifested in the negative excess voltage noise, i.e., the voltage fluctuations under high-field transport conditions can be less than in equilibrium.

410 - Phase transitions induced by coloured voltage noise in nerve membranes

Quantitative conditions are derived under which electrically excitable membranes can undergo a phase transition induced by an externally applied voltage noise. The results obtained for a non-cooperative and a cooperative form of the two-state model are compared. © 1981.

Mathematical models on the impact of noise and dyadic molecular structures on the properties of a cardiac myocyte

In cardiac myocytes (heart muscle cells), coupling of electric signal known as the action potential to contraction of the heart depends crucially on calcium-induced calcium release (CICR) in a microdomain known as the dyad. During CICR, the peak number of free calcium ions (Ca) present in the dyad is small, typically estimated to be within range 1-100. Since the free Ca ions mediate CICR, noise in Ca signaling due to the small number of free calcium ions influences Excitation-Contraction (EC) coupling gain. Noise in Ca signaling is only one noise type influencing cardiac myocytes, e.g., ion channels playing a central role in action potential propagation are stochastic machines, each of which gates more or less randomly, which produces gating noise present in membrane currents. How various noise sources influence macroscopic properties of a myocyte, how noise is attenuated and taken advantage of are largely open questions. In this thesis, the impact of noise on CICR, EC coupling and, more generally, macroscopic properties of a cardiac myocyte is investigated at multiple levels of detail using mathematical models. Complementarily to the investigation of the impact of noise on CICR, computationally-efficient yet spatially-detailed models of CICR are developed. The results of this thesis show that (1) gating noise due to the high-activity mode of L-type calcium channels playing a major role in CICR may induce early after-depolarizations associated with polymorphic tachycardia, which is a frequent precursor to sudden cardiac death in heart failure patients; (2) an increased level of voltage noise typically increases action potential duration and it skews distribution of action potential durations toward long durations in cardiac myocytes; and that (3) while a small number of Ca ions mediate CICR, Excitation-Contraction coupling is robust against this noise source, partly due to the shape of ryanodine receptor protein structures present in the cardiac dyad.

Investigations of noise and of quantum interference in proximity effect bridges

This work reports investigations upon weakly superconducting proximity effect bridges. These bridges, which exhibit the Josephson effects, are produced by bisecting a superconductor with a short (<1µ) region of material whose superconducting transition temperature is below that of the adjacent superconductors. These bridges are fabricated from layered refractory metal thin films whose transition temperature will depend upon the thickness ratio of the materials involved. The thickness ratio is changed in the area of the bridge to lower its transition temperature. This is done through novel photolithographic techniques described in the text, Chapter 2.

If two such proximity effect bridges are connected in parallel, they form a quantum interferometer. The maximum zero voltage current through this circuit is periodically modulated by the magnetic flux through the circuit. At a constant bias current, the modulation of the critical current produces a modulation in the dc voltage across the bridge. This change in dc voltage has been found to be the result of a change in the internal dissipation in the device. A simple model using lumped circuit theory and treating the bridges as quantum oscillators of frequency ω = 2eV/h, where V is the time average voltage across the device, has been found to adequately describe the observed voltage modulation.

The quantum interferometers have been converted to a galvanometer through the inclusion of an integral thin film current path which couples magnetic flux through the interferometer. Thus a change in signal current produces a change in the voltage across the interferometer at a constant bias current. This work is described in Chapter 3 of the text.

The sensitivity of any device incorporating proximity effect bridges will ultimately be determined by the fluctuations in their electrical parameters. He have measured the spectral power density of the voltage fluctuations in proximity effect bridges using a room temperature electronics and a liquid helium temperature transformer to match the very low (~ 0.1 Ω) impedances characteristic of these devices.

We find the voltage noise to agree quite well with that predicted by phonon noise in the normal conduction through the bridge plus a contribution from the superconducting pair current through the bridge which is proportional to the ratios of this current to the time average voltage across the bridge. The total voltage fluctuations are given by <V^2(f ) > = 4kTR^2_d I/V where R_d is the dynamic resistance, I the total current, and V the voltage across the bridge . An additional noise source appears with a strong 1/f^(n) dependence , 1.5 < n < 2, if the bridges are fabricated upon a glass substrate. This excess noise, attributed to thermodynamic temperature fluctuations in the volume of the bridge, increases dramatically on a glass substrate due to the greatly diminished thermal diffusivity of the glass as compared to sapphire.

Characterization of hot-electron effects on flicker noise in III-V nitride based heterojunctions

We report experiments on hot-electron stressing in commercial III-V nitride based heterojunction fight-emitting diodes. Stressing currents ranging from 100 mA to 200 mA were used. Degradations in the device properties were investigated through detailed studies of the I-V characteristics, electroluminescence, Deep-Level Transient Fourier Spectroscopy and flicker noise. Our experimental data demonstrated significant distortions in the I-V characteristics. The room temperature electroluminescence of the devices exhibited 25% decrement in the peak emission intensity. Concentration of the deep-levels was examined by measuring the Deep-Level Transient Fourier Spectroscopy, which indicated an increase in the density of deep-traps from 2.7 x 10(13) cm(-3) to 4.21 x 10(13) cm(-3) at E-1 = E-C - 1.1eV. The result is consistent with our study of 1/f noise, which exhibited up to three orders of magnitude increase in the voltage noise power spectra. Our experiments show large increase in both the interface traps and deep-levels resulted from hot-carrier stressing.

Low-Frequency Noise in Field-Effect Devices Functionalized With Dendrimer/Carbon-Nanotube Multilayers

Low-frequency noise in an electrolyte-insulator- semiconductor (EIS) structure functionalized with multilayers of polyamidoamine (PAMAM) dendrimer and single-walled carbon nanotubes (SWNT) is studied. The noise spectral density exhibits 1/f(gamma) dependence with the power factor of gamma approximate to 0.8 and gamma = 0.8-1.8 for the bare and functionalized EIS sensor, respectively. The gate-voltage noise spectral density is practically independent of the pH value of the solution and increases with increasing gate voltage or gate-leakage current. It has been revealed that functionalization of an EIS structure with a PAMAM/SWNTs multilayer leads to an essential reduction of the 1/f noise. To interpret the noise behavior in bare and functionalized EIS devices, a gate-current noise model for capacitive EIS structures based on an equivalent flatband-voltage fluctuation concept has been developed.

Revisiting the Classics to recover the Physical Sense in electrical noise

This paper shows a physically cogent model for electrical noise in resistors that has been obtained from Thermodynamical reasons. This new model derived from the works of Johnson and Nyquist also agrees with the Quantum model for noisy systems handled by Callen and Welton in 1951, thus unifying these two Physical viewpoints. This new model is a Complex or 2-D noise model based on an Admittance that considers both Fluctuation and Dissipation of electrical energy to excel the Real or 1-D model in use that only considers Dissipation. By the two orthogonal currents linked with a common voltage noise by an Admittance function, the new model is shown in frequency domain. Its use in time domain allows to see the pitfall behind a paradox of Statistical Mechanics about systems considered as energy-conserving and deterministic on the microscale that are dissipative and unpredictable on the macroscale and also shows how to use properly the Fluctuation-Dissipation Theorem.

Studies of high DC current induced degradation in III-V nitride based heterojunctions

We report experiments on high de current stressing in commercial III-V nitride based heterojunction light-emitting diodes. Stressing currents ranging from 100 mA to 200 mA were used. Degradations in the device properties were investigated through detailed studies of the current-voltage (I-V) characteristics, electroluminescence, deep-level transient Fourier spectroscopy and flicker noise. Our experimental data demonstrated significant distortions in the I-V characteristics subsequent to electrical stressing. The room temperature electro-luminescence of the devices exhibited a 25% decrement in the peak emission intensity. Concentration of the deep-levels was examined by deep-level transient Fourier spectroscopy, which indicated an increase in the density of deep-traps from 2.7 x 10(13) cm(-3) to 4.2 x 10(13) cm(-3) at E-1 = E-C - 1.1 eV. The result is consistent with our study of 1/f noise, which exhibited up to three orders of magnitude increase in the voltage noise power spectra. These traps are typically located at energy levels beyond the range that can be characterized by conventional techniques including DLTS. The two experiments, therefore, provide a more complete picture of trap generation due to high dc current stressing.

A simplified and higher dynamic range version of the J(1) ... J(4) method for optical phase measurements

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

Interferometric measurements of nanometric displacements in a Piezoelectric Flextensional Actuator by using the new J1...J5 method

In this work, nanometric displacement amplitudes of a Piezoelectric Flextensional Actuator (PFA) designed using the topology optimization technique and operating in its linear range are measured by using a homodyne Michelson interferometer. A new improved version of the J1...J4 method for optical phase measurements, named J1...J5 method, is presented, which is of easier implementation than the original one. This is a passive phase detection scheme, unaffected by signal fading, source instabilities and changes in visibility. Experimental results using this improvement were compared with those obtained by using the J1... J4, J1...J6(pos) and J1...J 6(neg) methods, concluding that the dynamic range is increased while maintaining the sensitivity. Analysis based on the 1/f voltage noise and random fading show the new method is more stable to phase drift than all those methods. © 2012 IEEE.

Physical Design Methodologies for Low Power and Reliable 3D ICs

As the semiconductor industry struggles to maintain its momentum down the path following the Moore's Law, three dimensional integrated circuit (3D IC) technology has emerged as a promising solution to achieve higher integration density, better performance, and lower power consumption. However, despite its significant improvement in electrical performance, 3D IC presents several serious physical design challenges. In this dissertation, we investigate physical design methodologies for 3D ICs with primary focus on two areas: low power 3D clock tree design, and reliability degradation modeling and management. Clock trees are essential parts for digital system which dissipate a large amount of power due to high capacitive loads. The majority of existing 3D clock tree designs focus on minimizing the total wire length, which produces sub-optimal results for power optimization. In this dissertation, we formulate a 3D clock tree design flow which directly optimizes for clock power. Besides, we also investigate the design methodology for clock gating a 3D clock tree, which uses shutdown gates to selectively turn off unnecessary clock activities. Different from the common assumption in 2D ICs that shutdown gates are cheap thus can be applied at every clock node, shutdown gates in 3D ICs introduce additional control TSVs, which compete with clock TSVs for placement resources. We explore the design methodologies to produce the optimal allocation and placement for clock and control TSVs so that the clock power is minimized. We show that the proposed synthesis flow saves significant clock power while accounting for available TSV placement area. Vertical integration also brings new reliability challenges including TSV's electromigration (EM) and several other reliability loss mechanisms caused by TSV-induced stress. These reliability loss models involve complex inter-dependencies between electrical and thermal conditions, which have not been investigated in the past. In this dissertation we set up an electrical/thermal/reliability co-simulation framework to capture the transient of reliability loss in 3D ICs. We further derive and validate an analytical reliability objective function that can be integrated into the 3D placement design flow. The reliability aware placement scheme enables co-design and co-optimization of both the electrical and reliability property, thus improves both the circuit's performance and its lifetime. Our electrical/reliability co-design scheme avoids unnecessary design cycles or application of ad-hoc fixes that lead to sub-optimal performance. Vertical integration also enables stacking DRAM on top of CPU, providing high bandwidth and short latency. However, non-uniform voltage fluctuation and local thermal hotspot in CPU layers are coupled into DRAM layers, causing a non-uniform bit-cell leakage (thereby bit flip) distribution. We propose a performance-power-resilience simulation framework to capture DRAM soft error in 3D multi-core CPU systems. In addition, a dynamic resilience management (DRM) scheme is investigated, which adaptively tunes CPU's operating points to adjust DRAM's voltage noise and thermal condition during runtime. The DRM uses dynamic frequency scaling to achieve a resilience borrow-in strategy, which effectively enhances DRAM's resilience without sacrificing performance. The proposed physical design methodologies should act as important building blocks for 3D ICs and push 3D ICs toward mainstream acceptance in the near future.

Wide Voltage Input Receiver with Hysteresis Characteristic to Reduce Input Signal Noise Effect

In this paper, an input receiver with a hysteresis characteristic that can work at voltage levels between 0.9 V and 5 V is proposed. The input receiver can be used as a wide voltage range Schmitt trigger also. At the same time, reliable circuit operation is ensured. According to the research findings, this is the first time a wide voltage range Schmitt trigger is being reported. The proposed circuit is compared with previously reported input receivers, and it is shown that the circuit has better noise immunity. The proposed input receiver ends the need for a separate Schmitt trigger and input buffer. The frequency of operation is also higher than that of the previously reported receiver. The circuit is simulated using HSPICE at 035-mu m standard thin oxide technology. Monte Carlo analysis is conducted at different process conditions, showing that the proposed circuit works well for different process conditions at different voltage levels of operation. A noise impulse of (V-CC/2) magnitude is added to the input voltage to show that the receiver receives the correct logic level even in the presence of noise. Here, V-CC is the fixed voltage supply of 3.3 V.

The use of current transformers for noise detection due to sparking in insulators strings in high voltage transmission lines

In a general way, in an electric power utility the current transformers (CT) are used to measurement and protection of transmission lines (TL) 1 The Power Line Carriers systems (PLC) are used for communication between electrical substations and transmission line protection. However, with the increasing use of optical fiber to communication (due mainly to its high data transmission rate and low signal-noise relation) this application loses potentiality. Therefore, other functions must be defined to equipments that are still in using, one of them is detecting faults (short-circuits) and transmission lines insulator strings damages 2. The purpose of this paper is to verify the possibility of using the path to the ground offered by the CTs instead of capacitive couplings / capacitive potential transformers to detect damaged insulators, since the current transformers are always present in all transmission lines (TL's) bays. To this a comparison between this new proposal and the PLC previous proposed system 2 is shown, evaluating the economical and technical points of view. ©2010 IEEE.

Dependence of Generation-Recombination Noise With Gate Voltage in FD SOI MOSFETs

A model for computing the generation-recombination noise due to traps within the semiconductor film of fully depleted silicon-on-insulator MOSFET transistors is presented. Dependence of the corner frequency of the Lorentzian spectra on the gate voltage is addressed in this paper, which is different to the constant behavior expected for bulk transistors. The shift in the corner frequency makes the characterization process easier. It helps to identify the energy position, capture cross sections, and densities of the traps. This characterization task is carried out considering noise measurements of two different candidate structures for single-transistor dynamic random access memory devices.

Efficient Voltage/Current Spike Reduction by Active Gate Signaling

This paper presents an Active Gate Signaling scheme to reduce voltage/current spikes across insulated gate power switches in hard switching power electronic circuits. Voltage and/or current spikes may cause EMI noise. In addition, they increase voltage/current stress on the switch. Traditionally, a higher gate resistance is chosen to reduce voltage/current spikes. Since the switching loss will increase remarkably, an active gate voltage control scheme is developed to improve efficiency of hard switching circuits while the undesirable voltage and/or current spikes are minimized.