Trapezoidal cross-sectional influence on FinFET threshold voltage and corner effects

Fin field effect transistors (FinFETS) are silicon-on-insulator (SOI) transistors with three-dimensional structures. As a result of some fabrication-process limitations (as nonideal anisotropic overetch) some FinFETs have inclined surfaces, which results in trapezoidal cross sections instead of rectangular sections, as expected. This geometric alteration results in some device issues, like carrier profile, threshold voltage, and corner effects. This work analyzes these consequences based on three-dimensional numeric simulation of several dual-gate and triple-gate FinFETs. The simulation results show that the threshold voltage depends on the sidewall inclination angle and that this dependence varies according to the body doping level. The corner effects also depend on the inclination angle and doping level. (C) 2008 The Electrochemical Society.

A new method of threshold voltage extraction via MOSFET gate-to-substrate capacitance measurement

A new method to extract MOSFET's threshold voltage VT by measurement of the gate-to-substrate capacitance C-gb of the transistor is presented. Unlike existing extraction methods based on I-V data, the measurement of C-gb does not require de drain current to now between drain and source thus eliminating the effects of source and drain series resistance R-S/D, and at the same time, retains a symmetrical potential profile across the channel. Experimental and simulation results on devices with different sizes are presented to justify the proposed method.

Temperature and time dependent threshold voltage characterization of AlGaN/GaN high electron mobility transistors

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Threshold voltages of SOI MuGFETs

The multiple-gate field-effect transistor (MuGFET) is a device with a gate folded on different sides of the channel region. They are one of the most promising technological solutions to create high-performance ultra-scaled SOI CMOS. In this work, the behavior of the threshold voltage in double-gate, triple-gate and quadruple-gate SOI transistors with different channel doping concentrations is studied through three-dimensional numerical simulation. The results indicated that for double-gate transistors, one or two threshold voltages can be observed, depending on the channel doping concentration. However, in triple-gate and quadruple-gate it is possible to observe up to four threshold voltages due to the corner effect and the different doping concentration between the top and bottom of the Fin. (C) 2008 Elsevier Ltd. All rights reserved.

Low-voltage driven ZnS:Mn MIS and MISIM thin film electroluminescent devices with Eu2O3 insulator layer

AC thin film electroluminescent devices of MIS and MISIM have been fabricated with a novel dielectric layer of Eu2O3 as an insulator. The threshold voltage for light emission is found to depend strongly on the frequency of excitation source in these devices. These devices are fabricated with an active layer of ZnS:Mn and a novel dielectric layer of Eu2O3 as an insulator. The observed frequency dependence of brightness-voltage characteristics has been explained on the basis of the loss characteristic of the insulator layer. Changes in the threshold voltage and brightness with variation in emitting or insulating film thickness have been investigated in metal-insulator-semiconductor (MIS) structures. It has been found that the decrease in brightness occurring with decreasing ZnS layer thickness can be compensated by an increase in brightness obtained by reducing the insulator thickness. The optimal condition for low threshold voltage and higher stability has been shown to occur when the active layer to insulator thickness ratio lies between one and two.

Bias-induced threshold voltages shifts in thin-film organic transistors

An investigation into the stability of metal-insulator-semiconductor (MIS) transistors based on alpha-sexithiophene is reported. In particular, the kinetics of the threshold voltage shift upon application of a gate bias has been determined. The kinetics follow stretched-hyperbola-type behavior, in agreement with the formalism developed to explain metastability in amorphous-silicon thin-film transistors. Using this model, quantification of device stability is possible. Temperature-dependent measurements show that there are two processes involved in the threshold voltage shift, one occurring at Tapproximate to220 K and the other at Tapproximate to300 K. The latter process is found to be sample dependent. This suggests a relation between device stability and processing parameters. (C) 2004 American Institute of Physics.

An In-Depth Study of the Barkhausen Emission Signal Properties of the Plastically Deformed Fe-2%Si Alloy

This paper presents the results of the in-depth study of the Barkhausen effect signal properties for the plastically deformed Fe-2%Si samples. The investigated samples have been deformed by cold rolling up to plastic strain epsilon(p) = 8%. The first approach consisted of time-domain-resolved pulse and frequency analysis of the Barkhausen noise signals whereas the complementary study consisted of the time-resolved pulse count analysis as well as a total pulse count. The latter included determination of time distribution of pulses for different threshold voltage levels as well as the total pulse count as a function of both the amplitude and the duration time of the pulses. The obtained results suggest that the observed increase in the Barkhausen noise signal intensity as a function of deformation level is mainly due to the increase in the number of bigger pulses.

Trapezoidal SOI FinFET analog parameters` dependence on cross-section shape

The trapezium is often a better approximation for the FinFET cross-section shape, rather than the design-intended rectangle. The frequent width variations along the vertical direction, caused by the etching process that is used for fin definition, may imply in inclined sidewalls and the inclination angles can vary in a significant range. These geometric variations may cause some important changes in the device electrical characteristics. This work analyzes the influence of the FinFET sidewall inclination angle on some relevant parameters for analog design, such as threshold voltage, output conductance, transconductance, intrinsic voltage gain (A V), gate capacitance and unit-gain frequency, through 3D numeric simulation. The intrinsic gain is affected by alterations in transconductance and output conductance. The results show that both parameters depend on the shape, but in different ways. Transconductance depends mainly on the sidewall inclination angle and the fixed average fin width, whereas the output conductance depends mainly on the average fin width and is weakly dependent on the sidewall inclination angle. The simulation results also show that higher voltage gains are obtained for smaller average fin widths with inclination angles that correspond to inverted trapeziums, i.e. for shapes where the channel width is larger at the top than at the transistor base because of the higher attained transconductance. When the channel top is thinner than the base, the transconductance degradation affects the intrinsic voltage gain. The total gate capacitances also present behavior dependent on the sidewall angle, with higher values for inverted trapezium shapes and, as a consequence, lower unit-gain frequencies.

Cryogenic operation of FinFETs aiming at analog applications

FinFETs are recognized as promising candidates for the CMOS nanometer era. In this paper the most recent results for cryogenic operation of FinFETs will be demonstrated with special emphasis on analog applications. Threshold voltage, subthreshold slope and carrier mobility will be studied. Also some important figures of merit for analog circuit operation as for readout electronics, such as transconductance, output conductance and intrinsic voltage gain will be covered. It is demonstrated that the threshold voltage of undoped narrow FinFETs is less temperature-dependent than for a planar single-gate device with similar doping concentration. The temperature reduction improves the transconductance over drain current ratio in any operational region. On the other hand, the output conductance is degraded when the temperature is reduced. The combination of these effects shows that the intrinsic gain of a L = 90 nm FinFET is degraded by 2 dB when the temperature reduces from 300 K to 100 K. (C) 2009 Elsevier Ltd. All rights reserved.

Temperature influence on the gate-induced floating body effect parameters in fully depleted SOI nMOSFETs

The temperature influence on the gate-induced floating body effect (GIFBE) in fully depleted (FD) silicon-on-insulator (SOI) nMOSFETs is investigated, based on experimental results and two-dimensional numerical simulations. The GIFBE behavior will be evaluated taking into account the impact of carrier recombination and of the effective electric field mobility degradation on the second peak in the transconductance (gm). This floating body effect is also analyzed as a function of temperature. It is shown that the variation of the studied parameters with temperature results in a ""C"" shape of the threshold voltage corresponding with the second peak in the gm curve. (C) 2008 Elsevier Ltd. All rights reserved.

Cryogenic Operation of Junctionless Nanowire Transistors

This letter presents the properties of nMOS junctionless nanowire transistors (JNTs) under cryogenic operation. Experimental results of drain current, subthreshold slope, maximum transconductance at low electric field, and threshold voltage, as well as its variation with temperature, are presented. Unlike in classical devices, the drain current of JNTs decreases when temperature is lowered, although the maximum transconductance increases when the temperature is lowered down to 125 K. An analytical model for the threshold voltage is proposed to explain the influence of nanowire width and doping concentration on its variation with temperature. It is shown that the wider the nanowire or the lower the doping concentration, the higher the threshold voltage variation with temperature.

A novel role for MNTB neuron dendrites in regulating action potential amplitude and cell excitability during repetitive firing

Principal cells of the medial nucleus of the trapezoid body (MNTB) are simple round neurons that receive a large excitatory synapse (the calyx of Held) and many small inhibitory synapses on the soma. Strangely, these neurons also possess one or two short tufted dendrites, whose function is unknown. Here we assess the role of these MNTB cell dendrites using patch-clamp recordings, imaging and immunohistochemistry techniques. Using outside-out patches and immunohistochemistry, we demonstrate the presence of dendritic Na(+) channels. Current-clamp recordings show that tetrodotoxin applied onto dendrites impairs action potential (AP) firing. Using Na(+) imaging, we show that the dendrite may serve to maintain AP amplitudes during high-frequency firing, as Na(+) clearance in dendritic compartments is faster than axonal compartments. Prolonged high-frequency firing can diminish Na(+) gradients in the axon while the dendritic gradient remains closer to resting conditions; therefore, the dendrite can provide additional inward current during prolonged firing. Using electron microscopy, we demonstrate that there are small excitatory synaptic boutons on dendrites. Multi-compartment MNTB cell simulations show that, with an active dendrite, dendritic excitatory postsynaptic currents (EPSCs) elicit delayed APs compared with calyceal EPSCs. Together with high- and low-threshold voltage-gated K(+) currents, we suggest that the function of the MNTB dendrite is to improve high-fidelity firing, and our modelling results indicate that an active dendrite could contribute to a `dual` firing mode for MNTB cells (an instantaneous response to calyceal inputs and a delayed response to non-calyceal dendritic excitatory postsynaptic potentials).

Photo-induced instability of nanocrystalline silicon TFTs

We examine the instability behavior of nanocrystalline silicon (nc-Si) thin-film transistors (TFTs) in the presence of electrical and optical stress. The change in threshold voltage and sub-threshold slope is more significant under combined bias-and-light stress when compared to bias stress alone. The threshold voltage shift (Delta V-T) after 6 h of bias stress is about 7 times larger in the case with illumination than in the dark. Under bias stress alone, the primary instability mechanism is charge trapping at the semiconductor/insulator interface. In contrast, under combined bias-and-light stress, the prevailing mechanism appears to be the creation of defect states in the channel, and believed to take place in the amorphous phase, where the increase in the electron density induced by electrical bias enhances the non-radiative recombination of photo-excited electron-hole pairs. The results reported here are consistent with observations of photo-induced efficiency degradation in solar cells.

Field effect and light-assisted a-Si:H sensors for detection of ions in solution

In this paper we present an amorphous silicon device that can be used in two operation modes to measure the concentration of ions in solution. While crystalline devices present a higher sensitivity, their amorphous counterpart present a much lower fabrication cost, thus enabling the production of cheap disposable sensors for use, for example, in the food industry. The devices were fabricated on glass substrates by the PECVD technique in the top gate configuration, where the metallic gate is replaced by an electrolytic solution with an immersed Ag/AgCl reference electrode. Silicon nitride is used as gate dielectric enhancing the sensitivity and passivation layer used to avoid leakage and electrochemical reactions. In this article we report on the semiconductor unit, showing that the device can be operated in a light-assisted mode, where changes in the pH produce changes on the measured ac photocurrent. In alternative the device can be operated as a conventional ion selective field effect device where changes in the pH induce changes in the transistor's threshold voltage.