System level design space exploration for MPSoC : methods, algorithms and new infrastructure

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ESys.Net : a new .Net based system-level design environment

Mémoire numérisé par la Direction des bibliothèques de l'Université de Montréal.

ESys.Net : a new .Net based system-level design environment

Mémoire numérisé par la Direction des bibliothèques de l'Université de Montréal.

System level DSP synthesis using voltage overscaling, unequal error protection & adaptive quality tuning

In this paper, we propose a system level design approach considering voltage over-scaling (VOS) that achieves error resiliency using unequal error protection of different computation elements, while incurring minor quality degradation. Depending on user specifications and severity of process variations/channel noise, the degree of VOS in each block of the system is adaptively tuned to ensure minimum system power while providing "just-the-right" amount of quality and robustness. This is achieved, by taking into consideration system level interactions and ensuring that under any change of operating conditions only the "lesscrucial" computations, that contribute less to block/system output quality, are affected. The design methodology applied to a DCT/IDCT system shows large power benefits (up to 69%) at reasonable image quality while tolerating errors induced by varying operating conditions (VOS, process variations, channel noise). Interestingly, the proposed IDCT scheme conceals channel noise at scaled voltages. ©2009 IEEE.

HERQULES:System level cross-layer design exploration for efficient energy-quality trade-offs

In this paper, we present a unique cross-layer design framework that allows systematic exploration of the energy-delay-quality trade-offs at the algorithm, architecture and circuit level of design abstraction for each block of a system. In addition, taking into consideration the interactions between different sub-blocks of a system, it identifies the design solutions that can ensure the least energy at the "right amount of quality" for each sub-block/system under user quality/delay constraints. This is achieved by deriving sensitivity based design criteria, the balancing of which form the quantitative relations that can be used early in the system design process to evaluate the energy efficiency of various design options. The proposed framework when applied to the exploration of energy-quality design space of the main blocks of a digital camera and a wireless receiver, achieves 58% and 33% energy savings under 41% and 20% error increase, respectively. © 2010 ACM.

Performance analysis of 4G wireless networks using system level simulator

In the last decade, mobile wireless communications have witnessed an explosive growth in the user’s penetration rate and their widespread deployment around the globe. In particular, a research topic of particular relevance in telecommunications nowadays is related to the design and implementation of mobile communication systems of 4th generation (4G). 4G networks will be characterized by the support of multiple radio access technologies in a core network fully compliant with the Internet Protocol (all IP paradigms). Such networks will sustain the stringent quality of service (QoS) requirements and the expected high data rates from the type of multimedia applications (i.e. YouTube and Skype) to be available in the near future. Therefore, 4G wireless communications system will be of paramount importance on the development of the information society in the near future. As 4G wireless services will continue to increase, this will put more and more pressure on the spectrum availability. There is a worldwide recognition that methods of spectrum managements have reached their limit and are no longer optimal, therefore new paradigms must be sought. Studies show that most of the assigned spectrum is under-utilized, thus the problem in most cases is inefficient spectrum management rather spectrum shortage. There are currently trends towards a more liberalized approach of spectrum management, which are tightly linked to what is commonly termed as Cognitive Radio (CR). Furthermore, conventional deployment of 4G wireless systems (one BS in cell and mobile deploy around it) are known to have problems in providing fairness (users closer to the BS are more benefited relatively to the cell edge users) and in covering some zones affected by shadowing, therefore the use of relays has been proposed as a solution. To evaluate and analyse the performances of 4G wireless systems software tools are normally used. Software tools have become more and more mature in recent years and their need to provide a high level evaluation of proposed algorithms and protocols is now more important. The system level simulation (SLS) tools provide a fundamental and flexible way to test all the envisioned algorithms and protocols under realistic conditions, without the need to deal with the problems of live networks or reduced scope prototypes. Furthermore, the tools allow network designers a rapid collection of a wide range of performance metrics that are useful for the analysis and optimization of different algorithms. This dissertation proposes the design and implementation of conventional system level simulator (SLS), which afterwards enhances for the 4G wireless technologies namely cognitive Radios (IEEE802.22) and Relays (IEEE802.16j). SLS is then used for the analysis of proposed algorithms and protocols.

Reduced-order modelling, circuit-level design and SOI fabrication of microelectromechanical resonators

This thesis deals with two important research aspects concerning radio frequency (RF) microresonators and switches. First, a new approach for compact modeling and simulation of these devices is presented. Then, a combined process flow for their simultaneous fabrication on a SOI substrate is proposed. Compact models for microresonators and switches are extracted by applying mathematical model order reduction (MOR) to the devices finite element (FE) description in ANSYS c° . The behaviour of these devices includes forms of nonlinearities. However, an approximation in the creation of the FE model is introduced, which enables the use of linear model order reduction. Microresonators are modeled with the introduction of transducer elements, which allow for direct coupling of the electrical and mechanical domain. The coupled system element matrices are linearized around an operating point and reduced. The resulting macromodel is valid for small signal analysis around the bias point, such as harmonic pre-stressed analysis. This is extremely useful for characterizing the frequency response of resonators. Compact modelling of switches preserves the nonlinearity of the device behaviour. Nonlinear reduced order models are obtained by reducing the number of nonlinearities in the system and handling them as input to the system. In this way, the system can be reduced using linear MOR techniques and nonlinearities are introduced directly in the reduced order model. The reduction of the number of system nonlinearities implies the approximation of all distributed forces in the model with lumped forces. Both for microresonators and switches, a procedure for matrices extraction has been developed so that reduced order models include the effects of electrical and mechanical pre-stress. The extraction process is fast and can be done automatically from ANSYS binary files. The method has been applied for the simulation of several devices both at devices and circuit level. Simulation results have been compared with full model simulations, and, when available, experimental data. Reduced order models have proven to conserve the accuracy of finite element method and to give a good description of the overall device behaviour, despite the introduced approximations. In addition, simulation is very fast, both at device and circuit level. A combined process-flow for the integrated fabrication of microresonators and switches has been defined. For this purpose, two processes that are optimized for the independent fabrication of these devices are merged. The major advantage of this process is the possibility to create on-chip circuit blocks that include both microresonators and switches. An application is, for example, aswitched filter bank for wireless transceiver. The process for microresonators fabrication is characterized by the use of silicon on insulator (SOI) wafers and on a deep reactive ion etching (DRIE) step for the creation of the vibrating structures in single-crystal silicon and the use of a sacrificial oxide layer for the definition of resonator to electrode distance. The fabrication of switches is characterized by the use of two different conductive layers for the definition of the actuation electrodes and by the use of a photoresist as a sacrificial layer for the creation of the suspended structure. Both processes have a gold electroplating step, for the creation of the resonators electrodes, transmission lines and suspended structures. The combined process flow is designed such that it conserves the basic properties of the original processes. Neither the performance of the resonators nor the performance of the switches results affected by the simultaneous fabrication. Moreover, common fabrication steps are shared, which allows for cheaper and faster fabrication.

System Engineering Approach to Initial Design of LEO Remote Sensing Missions

The satellite remote sensing missions are essential for long-term research around the condition of the earth resources and environment. On the other hand, in recent years the application of microsatellites is of interest in many space programs for their less cost and response time. In microsatellite remote sensing missions there are tight interrelations between different requirements such as orbital altitude, revisit time, mission life and spatial resolution. Also, all of these requirements can affect the whole system level design characteristics. In this work, the remote sensing microsatellite sizing process is divided into three major design disciplines; a) orbit design, b) payload sizing and c) bus sizing. Finally, some specific design cases are investigated inside the design space for evaluating the effect of different design variables on the satellite total mass. Considering the results of the work, it is concluded that applying a systematic approach at the initial design phase of such projects provides a good insight to the not clearly seen interactions inside their highly extended design space

An automated failure mode and effect analysis based on high-level design specificication with behavior trees

Formal methods have significant benefits for developing safety critical systems, in that they allow for correctness proofs, model checking safety and liveness properties, deadlock checking, etc. However, formal methods do not scale very well and demand specialist skills, when developing real-world systems. For these reasons, development and analysis of large-scale safety critical systems will require effective integration of formal and informal methods. In this paper, we use such an integrative approach to automate Failure Modes and Effects Analysis (FMEA), a widely used system safety analysis technique, using a high-level graphical modelling notation (Behavior Trees) and model checking. We inject component failure modes into the Behavior Trees and translate the resulting Behavior Trees to SAL code. This enables us to model check if the system in the presence of these faults satisfies its safety properties, specified by temporal logic formulas. The benefit of this process is tool support that automates the tedious and error-prone aspects of FMEA.

Moderation as judgement practice: Reconciling system level accountability and local level practice

Internationally, recognition of the role of assessment to inform the learning process has received much attention in recent years. Assessment for learning, not just of learning is being supported by an increasing body of literature providing strategies that teachers and their students can incorporate to support the learning process (Assessment Reform Group, 2002; Broadfoot & Black, 2004; James, 2006). Concurrently there has been an increase internationally in systemic accountability requirements of schools in terms of student results. The convergence of these two movements has resulted in some education systems promoting standards-driven reform involving authentic assessment and a re-examination of the relationship between the teacher and the student in the learning process. In this context standards are intended to be used as the basis for judgements of student achievement; while the results from assessment tasks are meant to both inform the teaching/learning process, and to report and track student progress. In such system, the role and reliability of teacher judgement takes centre stage.

System level tests of transformer differential protection using an IEC 61850 process bus

The IEC 61850 family of standards for substation communication systems were released in the early 2000s, and include IEC 61850-8-1 and IEC 61850-9-2 that enable Ethernet to be used for process-level connections between transmission substation switchyards and control rooms. This paper presents an investigation of process bus protection performance, as the in-service behavior of multi-function process buses is largely unknown. An experimental approach was adopted that used a Real Time Digital Simulator and 'live' substation automation devices. The effect of sampling synchronization error and network traffic on transformer differential protection performance was assessed and compared to conventional hard-wired connections. Ethernet was used for all sampled value measurements, circuit breaker tripping, transformer tap-changer position reports and Precision Time Protocol synchronization of sampled value merging unit sampling. Test results showed that the protection relay under investigation operated correctly with process bus network traffic approaching 100% capacity. The protection system was not adversely affected by synchronizing errors significantly larger than the standards permit, suggesting these requirements may be overly conservative. This 'closed loop' approach, using substation automation hardware, validated the operation of protection relays under extreme conditions. Digital connections using a single shared Ethernet network outperformed conventional hard-wired solutions.

Teaching games level design using the StarCraft II editor

Level design is often characterised as “where the rubber hits the road” in game development. It is a core area of games design, alongside design of game rules and narrative. However, there is a lack of literature dedicated to documenting teaching games design, let alone the more specialised topic of level design. Furthermore, there is a lack of formal frameworks for best practice in level design, as professional game developers often rely on intuition and previous experience. As a result, there is little for games design teachers to draw on when presented with the opportunity to teach a level design unit. In this paper, we discuss the design and implementation of a games level design unit in which students use the StarCraft II Galaxy Editor. We report on two cycles of an action research project, reflecting upon our experiences with respect to student feedback and peer review, and outlining our plans for improving the unit in years to come.

System integration design in MEMS - A case study of micromachined load cell

One of the critical issues in large scale commercial exploitation of MEMS technology is its system integration. In MEMS, a system design approach requires integration of varied and disparate subsystems with one of a kind interface. The physical scales as well as the magnitude of signals of various subsystems vary widely. Known and proven integration techniques often lead to considerable loss in advantages the tiny MEMS sensors have to offer. Therefore, it becomes imperative to think of the entire system at the outset, at least in terms of the concept design. Such design entails various aspects of the system ranging from selection of material, transduction mechanism, structural configuration, interface electronics, and packaging. One way of handling this problem is the system-in-package approach that uses optimized technology for each function using the concurrent hybrid engineering approach. The main strength of this design approach is the fast time to prototype development. In the present work, we pursue this approach for a MEMS load cell to complete the process of system integration for high capacity load sensing. The system includes; a micromachined sensing gauge, interface electronics and a packaging module representing a system-in-package ready for end characterization. The various subsystems are presented in a modular stacked form using hybrid technologies. The micromachined sensing subsystem works on principles of piezo-resistive sensing and is fabricated using CMOS compatible processes. The structural configuration of the sensing layer is designed to reduce the offset, temperature drift, and residual stress effects of the piezo-resistive sensor. ANSYS simulations are carried out to study the effect of substrate coupling on sensor structure and its sensitivity. The load cell system has built-in electronics for signal conditioning, processing, and communication, taking into consideration the issues associated with resolution of minimum detectable signal. The packaged system represents a compact and low cost solution for high capacity load sensing in the category of compressive type load sensor.