Nano-layer structure of silicon-on-insulator materials

Silicon-on-insulator (SOI) has been recognized as a promising semiconductor starting material for ICs where high speed and low power consumption are desirable, in addition to its unique applications in radiation-hardened circuits. In the present paper, three novel SOI nano-layer structures have been demonstrated. ULTRA-THIN SOI has been fabricated by separation by implantation of oxygen (SIMOX) technique at low oxygen ion energy of 45 keV and implantation dosage of 1.81017/cm2. The formed SOI layer is uniform with thickness of only 60 nm. This layer is of crystalline quality. and the interface between this layer and the buried oxide layer is very sharp, PATTERNED SOI nanostructure is illustrated by source and drain on insulator (DSOI) MOSFETs. The DSOI structure has been formed by selective oxygen ion implantation in SIMOX process. With the patterned SOI technology, the floating-body effect and self-heating effect, which occur in the conventional SOI devices, are significantly suppressed. In order to improve the total-dose irradiation hardness of SOI devices, SILICON ON INSULATING MULTILAYERS (SOIM) nano-structure is proposed. The buried insulating multilayers, which are composed of SiOx and SiNy layers, have been realized by implantation of nitride and oxygen ions into silicon in turn at different ion energies, followed by two steps of high temperature annealing process, respectively, Electric property investigation shows that the hardness to the total-dose irradiation of SOIM is remarkably superior to those of the conventional SIMOX SOI and the Bond-and-Etch-Back SOI.

Characterization of integrated Bragg gratings in silicon-on-insulator

Silicon-on-insulator (SOI) is rapidly emerging as a very promising material platform for integrated photonics. As it combines the potential for optoelectronic integration with the low-cost and large volume manufacturing capabilities and they are already accumulate a huge amount of applications in areas like sensing, quantum optics, optical telecommunications and metrology. One of the main limitations of current technology is that waveguide propagation losses are still much higher than in standard glass-based platform because of many reasons such as bends, surface roughness and the very strong optical confinement provided by SOI. Such high loss prevents the fabrication of efficient optical resonators and complex devices severely limiting the current potential of the SOI platform. The project in the first part deals with the simple waveguides loss problem and trying to link that with the polarization problem and the loss based on Fabry-Perot Technique. The second part of the thesis deals with the Bragg Grating characterization from again the point of view of the polarization effect which leads to a better stop-band use filters. To a better comprehension a brief review on the basics of the SOI and the integrated Bragg grating ends up with the fabrication techniques and some of its applications will be presented in both parts, until the end of both the third and the fourth chapters to some results which hopefully make its precedent explanations easier to deal with.

Growth of carbon nanotubes on fully processed silicon-on-insulator CMOS substrates.

This paper describes the growth of Carbon Nanotubes (CNTs) both aligned and non-aligned on fully processed CMOS substrates containing high temperature tungsten metallization. While the growth method has been demonstrated in fabricating CNT gas sensitive layers for high temperatures SOI CMOS sensors, it can be employed in a variety of applications which require the use of CNTs or other nanomaterials with CMOS electronics. In our experiments we have grown CNTs both on SOI CMOS substrates and SOI CMOS microhotplates (suspended on membranes formed by post-CMOS deep RIE etching). The fully processed SOI substrates contain CMOS devices and circuits and additionally, some wafers contained high current LDMOSFETs and bipolar structures such as Lateral Insulated Gate Bipolar Transistors. All these devices were used as test structures to investigate the effect of additional post-CMOS processing such as CNT growth, membrane formation, high temperature annealing, etc. Electrical characterisation of the devices with CNTs were performed along with SEM and Raman spectroscopy. The CNTs were grown both at low and high temperatures, the former being compatible with Aluminium metallization while the latter being possible through the use of the high temperature CMOS metallization (Tungsten). In both cases we have found that there is no change in the electrical behaviour of the CMOS devices, circuits or the high current devices. A slight degradation of the thermal performance of the CMOS microhotplates was observed due to the extra heat dissipation path created by the CNT layers, but this is expected as CNTs exhibit a high thermal conductance. In addition we also observed that in the case of high temperature CNT growth a slight degradation in the manufacturing yield was observed. This is especially the case where large area membranes with a diameter in excess of 500 microns are used.

Analytic model for turn off in the silicon-on-insulator LIGBT

Lateral insulated gate bipolar transistors (LIGBTs) in silicon-on-insulator (SOI) show a unique turn off characteristic when compared to junction-isolated RESURF LIGBTs or vertical IGBTs. The turn off characteristic shows an extended `terrace' where, after the initial fast transient characteristic of IGBTs due to the loss of the electron current, the current stays almost at the same value for an extended period of time, before suddenly dropping to zero. In this paper, we show that this terrace arises because there is a value of LIGBT current during switch off where the rate of expansion of the depletion region with respect to the anode current is infinite. Once this level of anode current is approached, the depletion region starts to expand very rapidly, and is only stopped when it reaches the n-type buffer layer surrounding the anode. Once this happens, the current rapidly drops to zero. A quasi-static analytic model is derived to explain this behaviour. The analytically modelled turn off characteristic agrees well with that found by numerical simulation.

Electrical conduction and optical properties of doped silicon-on-insulator photonic crystals

We investigate the electrical properties of silicon-on-insulator (SOI) photonic crystals as a function of both doping level and air filling factor. The resistance trends can be clearly explained by the presence of a depletion region around the sidewalls of the holes that is caused by band pinning at the surface. To understand the trade-off between the carrier transport and the optical losses due to free electrons in the doped SOI, we also measured the resonant modes of L3 photonic crystal nanocavities and found that surprisingly high doping levels, up to 1018 / cm3, are acceptable for practical devices with Q factors as high as 4× 104. © 2011 American Institute of Physics.

Enhanced light emission in active silicon-on-insulator photonic crystal slabs and slot waveguides

We present experimental measurements on Silicon-on-insulator (SOI) photonic crystal slabs with an active layer containing Er3+ ions-doped Silicon nanoclusters (Si-nc), showing strong enhancement of 1.54 μm emission at room temperature. We provide a systematic theoretical analysis to interpret such results. In order to get further insight, we discuss experimental data on the guided luminescence of unpatterned SOI planar slot waveguides, which show enhanced light emission in transverse-magnetic (TM) modes over transverse-electric (TE) ones. ©2007 IEEE.

Silicon on insulator thermodiode with extremely wide working temperature range

This paper presents for the first time the performance of a silicon-on-insulator (SOI) p-n thermodiode, which can operate in an extremely wide temperature range of 200°C to 700°C while maintaining its linearity. The thermodiode is embedded in a thin dielectric membrane underneath a tungsten microheater, which allows the diode characterization at very high temperature (> 800°C). The effect of the junction area (Aj) on the thermodiode linearity, sensitivity and self-heating is experimentally and theoretically investigated. Results on the long-term diode stability at high temperature are also reported. © 2013 IEEE.

Sub-nanosecond silicon-on-insulator optical micro-ring switch with low crosstalk

We demonstrate a sub-nanosecond electro-optical switch with low crosstalk in a silicon-on-insulator (SOI) dual-coupled micro-ring embedded with p-i-n diodes. A crosstalk of -23 dB is obtained in the 20-mu m-radius micro-ring with the well-designing asymmetric dual-coupling structure. By optimizations of the doping profiles and the fabrication processes, the sub-nanosecond switch-on/off time of < 400 ps is finally realized under an electrical pre-emphasized driving signal. This compact and fast-response micro-ring switch, which can be fabricated by complementary metal oxide semiconductor (CMOS) compatible technologies, have enormous potential in optical interconnects of multicore networks-on-chip.

Flexible Control of Light Propagation Using a Novel Photonic Crystal Hetero-Waveguide Based on Silicon-on-Insulator Slab

We demonstrate a photonic crystal hetero-waveguide based on silicon-on-insulator (SOI) slab, consisting of two serially connected width-reduced photonic crystal waveguides with different radii of the air holes adjacent to the waveguide. We show theoretically that the transmission window of the structure corresponds to the transmission range common to both waveguides and it is in inverse proportion to the discrepancy between the two waveguides. Also the group velocity of guided mode can be changed from low to high or high to low, depending on which port of the structure the signal is input from just in the same device, and the variation is proportional to the discrepancy between the two waveguides. Using this novel structure, we realize flexible control of transmission window and group velocity of guided mode simultaneously.

EPITAXIAL LATERAL OVERGROWTH OF GaN ON SILICON-ON-INSULATOR

From a single process, GaN layers were laterally overgrown on maskless stripe-patterned (111) silicon-on-insulator (SOI) substrates by metalorganic chemical vapor deposition. The influence of stress on the behavior of dislocations at the coalescence during growth was observed using transmission electron microscopy (TEM). Improvement of the crystallin equality of the GaN layer was demonstrated by TEM and micro-Raman spectroscopy. Furthermore, the benefits of SOI substrates for GaN growth are also discussed.

Design and Fabrication of a Photonic Crystal Channel Drop Filter Based on an Asymmetric Silicon-on-Insulator Slab

We report on the design and fabrication of a photonic crystal (PC) channel drop filter based on an asymmetric silicon-on-insulator (SOI) slab. The filter is composed of two symmetric stick-shape micro-cavities between two single-line-defect (W1) waveguides in a triangular lattice, and the phase matching condition for the filter to improve the drop efficiency is satisfied by modifying the positions and radii of the air holes around the micro-cavities. A sample is then fabricated by using electron beam lithography (EBL) and inductively coupled plasma (ICP) etching processes. The measured 0 factor of the filter is about 1140, and the drop efficiency is estimated to be 73% +/- 5% by fitting the transmission spectrum.

Thermo-optic variable optical attenuator with low power consumption fabricated on silicon-on-insulator by anisotropic chemical etching

A thermo-optic Mach-Zehnder (MZ) variable optical attenuator based on silicon waveguides with a large cross section was designed and fabricated on silicon-on-insulator (SOI) wafer. Multimode interferometers were used as power splitters and combiners in the MZ structure. In order to achieve a smooth interface, anisotropic chemical etching of silicon was used to fabricate the waveguides. Isolating grooves were introduced to reduce power consumption and device length. The device has a low power consumption of 210 mW and a response time of 50 mus. (C) 2004 Society of Photo-Optical Instrumentation Engineers.

Radiation hardness improvement of separation-by-implantation-of-oxygen/silicon-on-insulator material by nitrogen ion implantation

In our work, nitrogen ions were implanted into separation-by-implantation-of-oxygen (SIMOX) wafers to improve the radiation hardness of the SIMOX material. The experiments of secondary ion mass spectroscopy (SIMS) analysis showed that some nitrogen ions were distributed in the buried oxide layers and some others were collected at the Si/SiO2 interface after annealing. The results of electron paramagnetic resonance (EPR) suggested the density of the defects in the nitrided samples changed with different nitrogen ion implantation energies. Semiconductor-insulator-semiconductor (SIS) capacitors were made on the materials, and capacitance-voltage (C-V) measurements were carried out to confirm the results. The super total dose radiation tolerance of the materials was verified by the small increase of the drain leakage current of the metal-oxide-semiconductor field effect transistor with n-channel (NMOSFETs) fabricated on the materials before and after total dose irradiation. The optimum implantation energy was also determined.

Epitaxial SiC grown on silicon-on-insulator substrate with ultra-thin silicon-over-layer

We report on the comparative studies of epitaxial SiC films grown on silicon-on-insulator (SOI) and Si bulk substrates. The silicon-over-layer (SOL) on the SOI has been thinned down to different thicknesses, with the thinnest about 10 nm. It has been found that the full-width-at-half-maxim in the X-ray diffraction spectrum from the SiC films decreases as the SOL thickness decreases, indicating improved quality of the SiC film. A similar trend has also been found in the Raman spectrum. One of the potential explanations for the observation is strain accommodation by the ultra-thin SOI substrate. (c) 2005 Elsevier B.V. All rights reserved.

Stress reduction in GaN films on (111) silicon-on-insulator substrate grown by metal-organic chemical vapor deposition

The GaN film was grown on the (111) silicon-on-insulator (SOI) substrate by metal-organic chemical vapor deposition and then annealed in the deposition chamber. A multiple beam optical stress sensor was used for the in-situ stress measurement, and X-ray diffraction (XRD) and Raman spectroscopy were used for the characterization of GaN film. Comparing the characterization results of the GaN films on the bulk silicon and SOI substrates, we can see that the Raman spectra show the 3.0 cm(-1) frequency shift of E-2(TO), and the full width at half maximum of XRD rocking curves for GaN (0002) decrease from 954 arc see to 472 are sec. The results show that the SOI substrates can reduce the tensile stress in the GaN film and improve the crystalline quality. The annealing process is helpful for the stress reduction of the GaN film. The SOI substrate with the thin top silicon film is more effective than the thick top silicon film SOI substrate for the stress reduction. (C) 2007 Elsevier B.V. All rights reserved.