Heteroepitaxial growth and annealing of gamma-Al2O3 thin films on silicon

The gamma-Al2O3 films were grown on Si (100) substrates using the sources of TMA (Al (CH3)(3)) and O-2 by very low-pressure chemical vapor deposition (VLP-CVD). It has been found that the gamma-Al2O3 film has a mirror-like surface and the RMS was about 2.5nm. And the orientation relationship was gamma-Al2O3(100)/Si(100). The thickness uniformity of gamma-Al2O3 films for 2-inch epi-wafer was less than 5%. The X-ray diffraction (XRD) and reflection high-energy electron diffraction (RHEED) results show that the crystalline quality of the film was improved after the film was annealed at 1000degreesC in O-2 atmosphere. The high-frequency C-V and leakage current of Al/gamma-Al2O3/Si capacitor were also measured to verify the annealing effect of the film. The results show that the dielectric constant increased from 4 to 7 and the breakdown voltage for 65-nm-thick gamma-Al2O3 film on silicon increases from 17V to 53V.

V5+-doped Bi3.4Yb0.6Ti3O12 fatigue resistant ferroelectric thin films

In this paper, a serial of Bi3.4Yb0.6Ti3-xVxO12 (BYTV) thin film with different V5+ contents were deposited on Pt/Ti/SiO2/Si substrates by chemical solution deposition (CSD). The crystallized phase and electrical properties of the films were investigated using X-ray diffraction, polarization hysteresis loops, leakage current-voltage, and fatigue test. From our experimental results, it can be found that the ferroelectric properties can be improved greatly using V5+-doped in Bi3.4Yb0.6Ti3O12 (BYT) thin film, compared with the reported BYT thin film. The remanent polarization was enhanced and excellent leakage current characteristic with 10(-11)A at the bias voltage of 4V, which is much lower than the BYT thin film or some reported bismuth layer-structure ferroelectric films. Fatigue test shows that the fabricated films have good anti-fatigue characteristic after 10(10) switching cycles. (c) 2008 Published by Elsevier B.V.

High gain in hybrid transistors with BAlq(3)/Alq(3) isotype heterostructure emitter

We report the fabrication of permeable metal-base transistors based on bis(2-methyl-8-quinolinolato-N1,O8)-(1,1'-biphenyl-4-olato) aluminum (BAlq(3))/tri(8-hydroxyquinoline) aluminum (Alq(3)) isotype heterostructure as emitter layer. In this transistor, n-Si was used as the collector, LiF/Al as the emitter electrode, and Au/Al bilayer metal as the base. We show that the leakage current is greatly reduced in Al/n-Si/Au/Al/BAlq(3)/Alq(3)/LiF/Al devices with respect to Al/n-Si/Au/Al/Alq(3)/LiF/Al devices due to the utilization of BAlq(3)/Alq(3) isotype heterostructure emitter, leading to high common-base and common-emitter current gains at low driving voltages.

Enhanced charge collection in polymer photovoltaic cells by using an ethanol-soluble conjugated polyfluorene as cathode buffer layer

We report enhanced polymer photovoltaic (PV) cells by utilizing ethanol-soluble conjugated poly (9, 9-bis (6'-diethoxylphosphorylhexyl) fluorene) (PF-EP) as a buffer layer between the active layer consisting of poly(3-hexylthiophene)/[6, 6]-phenyl C61-butyric acid methyl ester blend and the Al cathode. Compared to the control PV cell with Al cathode, the introduction of PF-EP effectively increases the shunt resistance and improves the photo-generated charge collection since the slightly thicker semi-conducting PF-EP layer may restrain the penetration of Al atoms into the active layer that may result in increased leakage current and quench photo-generated excitons. The power conversion efficiency is increased ca. 8% compared to the post-annealed cell with Al cathode.

Organic thin-film transistors having inorganic/organic double gate insulators

Bottom-contact organic thin-film transistors (BC OTFTs) based on inorganic/organic double gate insulators were demonstrated. The double gate insulators consisted of tantalum pentoxide (Ta2O5) with high dielectric constant (kappa) as the first gate insulator and octadecyltrichlorosilane (OTS) with low kappa as the second gate insulator. The devices have carrier mobilities larger than 10(-2) cm(2)/V s, on/off current ratio greater than 10(5), and the threshold voltage of -14 V, which is threefold larger field-effect mobility and an order of magnitude larger on/off current ratio than the OTFTs with a Ta2O5 gate insulator. The leakage current was decreased from 2.4x10(-6) to 7.4x10(-8) A due to the introduction of the OTS second dielectric layer. The results demonstrated that using inorganic/organic double insulator as the gate dielectric layer is an effective method to fabricate OTFTs with improved electric characteristics.

Organic integrated pixels fabricated by a full evaporation method

An organic integrated pixel consisting of an organic light-emitting diode driven by an organic thin-film field-effect transistor (OTFT) was fabricated by a full evaporation method oil a transparent glass substrate. The OTFT was designed as a top-gate Structure, and the insulator is composed of a double-layer polymer of Nylon 6 and Teflon to lower the operation voltage and the gate-leakage current, and improve the device stability. The field-effect mobility of the OTFT is more than 0.5 cm(2) V-1 s(-1), and the on/off ratio is larger than 10(3). The brightness of the pixel reached as large as 300 cd m(-2) at a driving current of 50 mu A.

Improved performance by a double-insulator layer in organic thin-flim transistors

Organic thin film transistors based on pentacene are fabricated by the method of full evaporation. The thickness of insulator film can be controlled accurately, which influences the device operation voltage markedly. Compared to the devices with a single-insulator layer, the electric performance of devices by using a double-insulator as the gate dielectric has good improvement. It is found that the gate leakage current can be reduced over one order of magnitude, and the on-state current can be enhanced over one order of magnitude. The devices with double-insulator layer exhibit field-effect mobility as large as 0.14 cm(2)/Vs and near the zero threshold voltage. The results demonstrate that using proper double insulator as the gate dielectrics is an effective method to fabricate OTFTs with high electrical performance.

Bottom-contact organic field-effect transistors having low-dielectric layer under source and drain electrodes

An organic thin-film transistor (OTFT) having a low-dielectric polymer layer between gate insulator and source/drain electrodes is investigated. Copper phthalocyanine (CuPc), a well-known organic semiconductor, is used as an active layer to test performance of the device. Compared with bottom-contact devices, leakage current is reduced by roughly one order of magnitude, and on-state current is enhanced by almost one order of magnitude. The performance of the device is almost the same as that of a top-contact device. The low-dielectric polymer may play two roles to improve OTFT performance. One is that this structure influences electric-field distribution between source/drain electrodes and semiconductor and enhances charge injection. The other is that the polymer influences growth behavior of CuPc thin films and enhances physical connection between source/drain electrodes and semiconductor channel. Advantages of the OTFT having bottom-contact structure make it useful for integrated plastic electronic devices.

Multi-scale modelling of atomic layer deposition

High-permittivity ("high-k") dielectric materials are used in the transistor gate stack in integrated circuits. As the thickness of silicon oxide dielectric reduces below 2 nm with continued downscaling, the leakage current because of tunnelling increases, leading to high power consumption and reduced device reliability. Hence, research concentrates on finding materials with high dielectric constant that can be easily integrated into a manufacturing process and show the desired properties as a thin film. Atomic layer deposition (ALD) is used practically to deposit high-k materials like HfO2, ZrO2, and Al2O3 as gate oxides. ALD is a technique for producing conformal layers of material with nanometer-scale thickness, used commercially in non-planar electronics and increasingly in other areas of science and technology. ALD is a type of chemical vapor deposition that depends on self-limiting surface chemistry. In ALD, gaseous precursors are allowed individually into the reactor chamber in alternating pulses. Between each pulse, inert gas is admitted to prevent gas phase reactions. This thesis provides a profound understanding of the ALD of oxides such as HfO2, showing how the chemistry affects the properties of the deposited film. Using multi-scale modelling of ALD, the kinetics of reactions at the growing surface is connected to experimental data. In this thesis, we use density functional theory (DFT) method to simulate more realistic models for the growth of HfO2 from Hf(N(CH3)2)4/H2O and HfCl4/H2O and for Al2O3 from Al(CH3)3/H2O.Three major breakthroughs are discovered. First, a new reaction pathway, ’multiple proton diffusion’, is proposed for the growth of HfO2 from Hf(N(CH3)2)4/H2O.1 As a second major breakthrough, a ’cooperative’ action between adsorbed precursors is shown to play an important role in ALD. By this we mean that previously-inert fragments can become reactive once sufficient molecules adsorb in their neighbourhood during either precursor pulse. As a third breakthrough, the ALD of HfO2 from Hf(N(CH3)2)4 and H2O is implemented for the first time into 3D on-lattice kinetic Monte-Carlo (KMC).2 In this integrated approach (DFT+KMC), retaining the accuracy of the atomistic model in the higher-scale model leads to remarkable breakthroughs in our understanding. The resulting atomistic model allows direct comparison with experimental techniques such as X-ray photoelectron spectroscopy and quartz crystal microbalance.

Atomic layer deposition of interface control layers for the fabrication of III/V MOS devices

The continued advancement of metal oxide semiconductor field effect transistor (MOSFET) technology has shifted the focus from Si/SiO2 transistors towards high-κ/III-V transistors for high performance, faster devices. This has been necessary due to the limitations associated with the scaling of the SiO2 thickness below ~1 nm and the associated increased leakage current due to direct electron tunnelling through the gate oxide. The use of these materials exhibiting lower effective charge carrier mass in conjunction with the use of a high-κ gate oxide allows for the continuation of device scaling and increases in the associated MOSFET device performance. The high-κ/III-V interface is a critical challenge to the integration of high-κ dielectrics on III-V channels. The interfacial chemistry of the high-κ/III-V system is more complex than Si, due to the nature of the multitude of potential native oxide chemistries at the surface with the resultant interfacial layer showing poor electrical insulating properties when high-κ dielectrics are deposited directly on these oxides. It is necessary to ensure that a good quality interface is formed in order to reduce leakage and interface state defect density to maximise channel mobility and reduce variability and power dissipation. In this work, the ALD growth of aluminium oxide (Al2O3) and hafnium oxide (HfO2) after various surface pre-treatments was carried out, with the aim of improving the high-κ/III-V interface by reducing the Dit – the density of interface defects caused by imperfections such as dangling bonds, dimers and other unsatisfied bonds at the interfaces of materials. A brief investigation was performed into the structural and electrical properties of Al2O3 films deposited on In0.53Ga0.47As at 200 and 300oC via a novel amidinate precursor. Samples were determined to experience a severe nucleation delay when deposited directly on native oxides, leading to diminished functionality as a gate insulator due to largely reduced growth per cycle. Aluminium oxide MOS capacitors were prepared by ALD and the electrical characteristics of GaAs, In0.53Ga0.47As and InP capacitors which had been exposed to pre-pulse treatments from triethyl gallium and trimethyl indium were examined, to determine if self-cleaning reactions similar to those of trimethyl aluminium occur for other alkyl precursors. An improved C-V characteristic was observed for GaAs devices indicating an improved interface possibly indicating an improvement of the surface upon pre-pulsing with TEG, conversely degraded electrical characteristics observed for In0.53Ga0.47As and InP MOS devices after pre-treatment with triethyl gallium and trimethyl indium respectively. The electrical characteristics of Al2O3/In0.53Ga0.47As MOS capacitors after in-situ H2/Ar plasma treatment or in-situ ammonium sulphide passivation were investigated and estimates of interface Dit calculated. The use of plasma reduced the amount of interface defects as evidenced in the improved C-V characteristics. Samples treated with ammonium sulphide in the ALD chamber were found to display no significant improvement of the high-κ/III-V interface. HfO2 MOS capacitors were fabricated using two different precursors comparing the industry standard hafnium chloride process with deposition from amide precursors incorporating a ~1nm interface control layer of aluminium oxide and the structural and electrical properties investigated. Capacitors furnished from the chloride process exhibited lower hysteresis and improved C-V characteristics as compared to that of hafnium dioxide grown from an amide precursor, an indication that no etching of the film takes place using the chloride precursor in conjunction with a 1nm interlayer. Optimisation of the amide process was carried out and scaled samples electrically characterised in order to determine if reduced bilayer structures display improved electrical characteristics. Samples were determined to exhibit good electrical characteristics with a low midgap Dit indicative of an unpinned Fermi level

Novel processes, test structures and characterisation for future germanium technologies

In order to widely use Ge and III-V materials instead of Si in advanced CMOS technology, the process and integration of these materials has to be well established so that their high mobility benefit is not swamped by imperfect manufacturing procedures. In this dissertation number of key bottlenecks in realization of Ge devices are investigated; We address the challenge of the formation of low resistivity contacts on n-type Ge, comparing conventional and advanced rapid thermal annealing (RTA) and laser thermal annealing (LTA) techniques respectively. LTA appears to be a feasible approach for realization of low resistivity contacts with an incredibly sharp germanide-substrate interface and contact resistivity in the order of 10 -7 Ω.cm2. Furthermore the influence of RTA and LTA on dopant activation and leakage current suppression in n+/p Ge junction were compared. Providing very high active carrier concentration > 1020 cm-3, LTA resulted in higher leakage current compared to RTA which provided lower carrier concentration ~1019 cm-3. This is an indication of a trade-off between high activation level and junction leakage current. High ION/IOFF ratio ~ 107 was obtained, which to the best of our knowledge is the best reported value for n-type Ge so far. Simulations were carried out to investigate how target sputtering, dose retention, and damage formation is generated in thin-body semiconductors by means of energetic ion impacts and how they are dependent on the target physical material properties. Solid phase epitaxy studies in wide and thin Ge fins confirmed the formation of twin boundary defects and random nucleation growth, like in Si, but here 600 °C annealing temperature was found to be effective to reduce these defects. Finally, a non-destructive doping technique was successfully implemented to dope Ge nanowires, where nanowire resistivity was reduced by 5 orders of magnitude using PH3 based in-diffusion process.

6-T SRAM cell design with nanoscale double-gate SOI MOSFETs: impact of source/drain engineering and circuit topology

The impact of source/drain engineering on the performance of a six-transistor (6-T) static random access memory (SRAM) cell, based on 22 nm double-gate (DG) SOI MOSFETs, has been analyzed using mixed-mode simulation, for three different circuit topologies for low voltage operation. The trade-offs associated with the various conflicting requirements relating to read/write/standby operations have been evaluated comprehensively in terms of eight performance metrics, namely retention noise margin, static noise margin, static voltage/current noise margin, write-ability current, write trip voltage/current and leakage current. Optimal design parameters with gate-underlap architecture have been identified to enhance the overall SRAM performance, and the influence of parasitic source/drain resistance and supply voltage scaling has been investigated. A gate-underlap device designed with a spacer-to-straggle (s/sigma) ratio in the range 2-3 yields improved SRAM performance metrics, regardless of circuit topology. An optimal two word-line double-gate SOI 6-T SRAM cell design exhibits a high SNM similar to 162 mV, I-wr similar to 35 mu A and low I-leak similar to 70 pA at V-DD = 0.6 V, while maintaining SNM similar to 30% V-DD over the supply voltage (V-DD) range of 0.4-0.9 V.

Comparative analysis of the DC performance of DG MOSFETs on highly-doped and near-intrinsic silicon layers

A comparison of dc characteristics of fully depleted double-gate (DG) MOSFETs with respect to low-power circuit applications and device scaling has been performed by two-dimensional device simulation. Three different DG MOSFET structures including a conventional N+ polysilicon gate device with highly doped Si layer, an asymmetrical P+/N+ polysilicon gate device with low doped Si layer and a midgap metal gate device with low doped Si layer have been analysed. It was found that DG MOSFET with mid-gap metal, gates yields the best dc parameters for given off-state drain leakage current and highest immunity to the variation of technology parameters (gate length, gate oxide thickness and Si layer thickness). It is also found that an asymmetrical P+/N+ polysilicon gate DG MOSFET design offers comparable dc characteristics, but better parameter immunity to technology tolerances than a conventional DG MOSFET. (C) 2004 Elsevier Ltd. All rights reserved.

Electrical characterization of ALD Al2O3 and HfO2 films on germanium

Al2O3 and HfO2 films were deposited on germanium substrates by atomic layer deposition (ALD) and analyzed by MOS capacitor electrical characterization. In-situ plasma nitridation performed prior to ALD was found to improve the stability of the interface. For Al 2O3/GeON/Ge capacitors, a 450°C anneal in nitrogen ambient reduced hysteresis and oxide fixed charge to 90 mV and 1012 cm-2 respectively, with low leakage current density. On the contrary, degradation was observed for un-nitrided Al2O3/Ge capacitors after 300 and 400°C post-metal anneals. HfO2/GeON/Ge capacitors benefitted from a 400°C densification anneal but exhibited degradation after post-metal anneals at temperatures greater than 300°C. This degradation is attributed to the influence of Al electrodes on the HfO 2 gate stack. HfO2 is considered to be a suitable material for the gate stack and Al2O3 for the buried dielectric in a GeOI structure. ©The Electrochemical Society.