Comparative analysis of nanoscale MOS device architectures for RF applications

This paper provides valuable design insights for optimizing device parameters for nanoscale planar and vertical SOI MOSFETs. The suitability of nanoscale non-planar FinFETs and classical planar single and double gate SOI MOSFETs for rf applications is examined via extensive 3D device simulations and detailed interpretation. The origin of higher parasitic capacitance in FinFETs, compared to planar MOSFETs is examined. RF figures of merit for planar and vertical MOS devices are compared, based on layout-area calculations.

Nanoscale ferroelectrics machined from single crystals

This paper summarises some of the most recent work that has been done on nanoscale ferroelectrics as a result of a joint collaborative research effort involving groups in Queen's University Belfast, the University of Cambridge and the University of St. Andrews. Attempts have been made to observe fundamental effects of reduced size, and increasing morphological complexity, on ferroelectric behaviour by studying the functional response and domain characteristics in nanoscale single crystal material, whose size and morphology have been defined by Focused Ion Beam (FIB) patterning. This approach to nanoshape fabrication has allowed the following broad statements to be made: (i) in single crystal BaTiO3 sheets, permittivity and phase transition behaviour is not altered from that of bulk material down to a thickness of similar to 75 nm; (ii) in single crystal BaTiO3 sheets and nanowires changes in observed domain morphologies are consistent with large scale continuum modeling.

6-T SRAM cell design with nanoscale double-gate SOI MOSFETs: impact of source/drain engineering and circuit topology

The impact of source/drain engineering on the performance of a six-transistor (6-T) static random access memory (SRAM) cell, based on 22 nm double-gate (DG) SOI MOSFETs, has been analyzed using mixed-mode simulation, for three different circuit topologies for low voltage operation. The trade-offs associated with the various conflicting requirements relating to read/write/standby operations have been evaluated comprehensively in terms of eight performance metrics, namely retention noise margin, static noise margin, static voltage/current noise margin, write-ability current, write trip voltage/current and leakage current. Optimal design parameters with gate-underlap architecture have been identified to enhance the overall SRAM performance, and the influence of parasitic source/drain resistance and supply voltage scaling has been investigated. A gate-underlap device designed with a spacer-to-straggle (s/sigma) ratio in the range 2-3 yields improved SRAM performance metrics, regardless of circuit topology. An optimal two word-line double-gate SOI 6-T SRAM cell design exhibits a high SNM similar to 162 mV, I-wr similar to 35 mu A and low I-leak similar to 70 pA at V-DD = 0.6 V, while maintaining SNM similar to 30% V-DD over the supply voltage (V-DD) range of 0.4-0.9 V.

Source/drain extension region engineering in nanoscale double gate SOI MOSFETs: Novel design methodology for low-voltage analog applications

The present paper proposes for the first time, a novel design methodology based on the optimization of source/drain extension (SDE) regions to significantly improve the trade-off between intrinsic voltage gain (A(vo)) and cut-off frequency (f(T)) in nanoscale double gate (DG) devices. Our results show that an optimally designed 25 nm gate length SDE region engineered DG MOSFET operating at drain current of 10 mu A/mu m, exhibits up to 65% improvement in intrinsic voltage gain and 85% in cut-off frequency over devices designed with abrupt SIDE regions. The influence of spacer width, lateral source/drain doping gradient and symmetric as well as asymmetrically designed SDE regions on key analog figures of merit (FOM) such as transconductance (g(m)), transconductance-to-current ratio (g(m)/I-ds), Early voltage (V-EA), output conductance (g(ds)) and gate capacitances are examined in detail. The present work provides new opportunities for realizing future low-voltage/low-power analog circuits with nanoscale SDE engineered DG MOSFETs. (C) 2007 Elsevier B.V. All rights reserved.

Engineering source/drain extension regions in nanoscale double gate (DG) SOI MOSFETs: Analytical model and design considerations

In this paper, we propose for the first time, an analytical model for short channel effects in nanoscale source/drain extension region engineered double gate (DG) SOI MOSFETs. The impact of (i) lateral source/drain doping gradient (d), (ii) spacer width (s), (iii) spacer to doping gradient ratio (s/d) and (iv) silicon film thickness (T-si), on short channel effects - threshold voltage (V-th) and subthreshold slope (S), on-current (I-on), off-current (I-on) and I-on/I-off is extensively analysed by using the analytical model and 2D device simulations. The results of the analytical model confirm well with simulated data over the entire range of spacer widths, doping gradients and effective channel lengths. Results show that lateral source/drain doping gradient along with spacer width can not only effectively control short channel effects, thus presenting low off-current, but can also be optimised to achieve high values of on-currents. The present work provides valuable design insights in the performance of nanoscale DG Sol devices with optimal source/drain engineering and serves as a tool to optimise important device and technological parameters for 65 nm technology node and below. (c) 2006 Elsevier Ltd. All rights reserved.

Ferroelectrics at the Nanoscale

There are several factors which make the investigation and understanding of nanoscale ferroelectrics particularly timely and important. Firstly, there is a market pressure, primarily from the electronics industry, to integrate ferroelectrics into devices with progressive decreases in size and increases in morphological complexity. This is perhaps best illustrated through the roadmaps for product development in FeRAM (Ferroelectric Randorn Access Memory) where the need for increases in bit density will require a move from 2D planar capacitor structures to 3D trenched capacitors in the next few years. Secondly, there is opportunity for novel exploration, as it is only relatively recently that developments in thin film growth of complex oxides, self-assembly techniques and high-resolution 'top-down' patterning have converged to allow the fabrication of isolated and well-defined ferroelectric nanoshapes, the properties of which are not known. Thirdly, there is an expectation that the behaviour of small scale ferroelectrics will be different from bulk, as this group of functional materials is highly sensitive to boundary/surface conditions, which are expected to dominate the overall response when sizes are reduced into the nanoscale regime. This feature article attempts to introduce some of the current areas of discovery and debate surrounding studies on ferroelectrics at the nanoscale. The focus is directed primarily at the search for novel size-related properties and behaviour which are not necessarily observed in bulk.

Settling the ‘‘Dead Layer’’ Debate in Nanoscale Capacitors

Permittivity peaks in single crystal thin film capacitors are strongly suppressed compared to bulk in the case of Pt/SrTiO(3)/Pt, but are relatively unaffected in Pt/BaTiO(3)/Pt structures. This is consistent with the recent suggestion that subtle variations in interfacial bonding between the dielectric and electrode are critical in determining the presence or absence of inherent dielectric "dead layers".

An efficient neural network approach for nanoscale FinFET modelling and circuit simulation

The present paper demonstrates the suitability of artificial neural network (ANN) for modelling of a FinFET in nano-circuit simulation. The FinFET used in this work is designed using careful engineering of source-drain extension, which simultaneously improves maximum frequency of oscillation f(max) because of lower gate to drain capacitance, and intrinsic gain A(V0) = g(m)/g(ds), due to lower output conductance g(ds). The framework for the ANN-based FinFET model is a common source equivalent circuit, where the dependence of intrinsic capacitances, resistances and dc drain current I-d on drain-source V-ds and gate-source V-gs is derived by a simple two-layered neural network architecture. All extrinsic components of the FinFET model are treated as bias independent. The model was implemented in a circuit simulator and verified by its ability to generate accurate response to excitations not used during training. The model was used to design a low-noise amplifier. At low power (J(ds) similar to 10 mu A/mu m) improvement was observed in both third-order-intercept IIP3 (similar to 10 dBm) and intrinsic gain A(V0) (similar to 20 dB), compared to a comparable bulk MOSFET with similar effective channel length. This is attributed to higher ratio of first-order to third-order derivative of I-d with respect to gate voltage and lower g(ds), in FinFET compared to bulk MOSFET. Copyright (C) 2009 John Wiley & Sons, Ltd.

Biological consequences of nanoscale energy deposition near irradiated heavy atom nanoparticles

Gold nanoparticles (GNPs) are being proposed as contrast agents to enhance X-ray imaging and radiotherapy, seeking to take advantage of the increased X-ray absorption of gold compared to soft tissue. However, there is a great discrepancy between physically predicted increases in X-ray energy deposition and experimentally observed increases in cell killing. In this work, we present the first calculations which take into account the structure of energy deposition in the nanoscale vicinity of GNPs and relate this to biological outcomes, and show for the first time good agreement with experimentally observed cell killing by the combination of X-rays and GNPs. These results are not only relevant to radiotherapy, but also have implications for applications of heavy atom nanoparticles in biological settings or where human exposure is possible because the localised energy deposition high-lighted by these results may cause complex DNA damage, leading to mutation and carcinogenesis.

Domain Wall Propagation in Meso and Nanoscale Ferroelectrics

As part of an ongoing programme to evaluate the extent to which external morphology alters domain wall mobility in ferroelectrics, the electrical switching characteristics of single-crystal BaTiO3 nanorods and thin film plates have been measured and compared. It was found that ferroelectric nanorods were more readily switched than thin plates; increasing the shape constraint therefore appears to enhance switchability. This observation is broadly consistent with previous work, in which local notches patterned along the length of nanorods enhanced switching (McMillen et al 2010 Appl. Phys. Lett. 96 042904), while antinotches had the opposite effect (McQuaid et al 2010 Nano Lett. 10 3566). In this prior work, local enhancement and denudation of the electric field was expected at the notch and antinotch sites, respectively, and this was thought to be the reason for the differences in switching behaviour observed. However, for the simple nanorods and plates investigated here, no differences in the electric field distributions are expected. To rationalise the functional measurements, domain development during switching was imaged directly by piezoresponse force microscopy. A two-stage process was identified, in which narrow needle-like reverse domains initially form across the entire interelectrode gap and then subsequently coarsen through domain wall propagation perpendicular to the applied electric field. To be consistent with the electrical switching data, we suggest that the initial formation of needle domains occurs more readily in the nanorods than in the plates.

Exciton-Plasmon States in Nanoscale Materials: Breakdown of the Tamm-Dancoff Approximation

Within the Tamm-Dancoff approximation, ab initio approaches describe excitons as packets of electron-hole pairs propagating only forward in time. However, we show that in nanoscale materials excitons and plasmons hybridize, creating exciton-plasmon states where the electron-hole pairs oscillate back and forth in time. Then, as exemplified by the trans-azobenzene molecule and the carbon nanotubes, the Tamm-Dancoff approximation yields errors larger than the accuracy claimed in ab initio calculations. Instead, we propose a general and efficient approach that avoids the Tamm-Dancoff approximation, correctly describes excitons, plasmons, and exciton-plasmon states, and provides a good agreement with experimental results.