Fabrication of improved FD SOIMOSFETs for suppressing edge effect

FD SOI MOSFETs with MESA and Irradiated FD SOI MOSFETs with LOCOS isolation usually show the edge effect, that is, the leakage current called hump is generated in the subthreshold region. According to different reasons for generating the edge effect, rounded corner process and BTS structure are applied to improve device performance. The results indicate that the above two methods are effective to reduce the edge effect and qualified devices are fabricated successfully.

Monostable-Bistable Transition Logic Element (MOBILE) Model for Single-Electron Transistors

The traditional monostable-bistable transition logic element (MOBILE) structure is usually composed of resonant tunneling diodes (RTD). This letter describes a new type MOBILE structure consisting of single-electron transistors (i.e. SET-MOBILE). The analytical model of single-electron transistors ( SET) has been considered three states (including an excited state) of the discrete quantum energy levels. The simulation results show negative differential conductance (NDC) characteristics in I-DS-V-DS curve. The SET-MOBILE utilizing NDC characteristics can successfully realize the basic logic functions as the RTD-MOBILE.

Evolution of wetting layers in InAs/GaAs quantum-dot system studied by reflectance difference spectroscopy

The wetting layers (WL) in InAs/GaAs quantum-dot system have been studied by reflectance difference spectroscopy (RDS), in which two structures related to the heavy-hole (HH) and light-hole (LH) transitions in the WL have been observed. The evolution and segregation behaviors of WL during Stranski-Krastanow (SK) growth mode have been studied from the analysis of the WL-related optical transition energies. It has been found that the segregation coefficient of Indium atoms varies linearly with the InAs amount in WL. In addition, the effect of the growth temperature on the critical thickness for InAs island formation has also been studied. The critical thickness defined by the appearance of InAs dots, which is determined by AFM, shows a complex variation with the growth temperature. However, the critical thickness determined by RDS is almost constant in the range of 510-540 degrees C.

High epitaxial growth rate of 4H-SiC using TCS as silicon precursor

High homoepitaxial growth of 4H-SiC has been performed in a home-made horizontal hot wall CVD reactor on n-type 4H-SiC 8 degrees off-oriented substrates in the size of 10 mm x 10 mm, using trichlorosilane (TCS) as silicon precursor source together with ethylene as carbon precursor source. Cross-section Scanning Electron Microscopy (SEM), Raman scattering spectroscopy and Atomic Force Microscopy (AFM) were used to determine the growth rate, structural property and surface morphology, respectively. The growth rate reached to 23 mu m/h and the optimal epilayer was obtained at 1600 degrees C with TCS flow rate of 12 seem in C/Si of 0.42, which has a good surface morphology with a low Rms of 0.64 nm in 10 mu mx10 mu m area.

Operational Optimization of GaN Thin Film Growth Employing Numerical Simulation in a Showerhead MOCVD Reactor

A detailed reaction-tran sport model was studied in a showerhead reactor for metal organic chemical vapor deposition of GaN film by using computational fluid dynamics simulation. It was found that flat flow lines without swirl are crucial to improve the uniformity of the film growth, and thin temperature gradient above the suscptor can increase the film deposition rate. By above-mentioned research, we can employ higher h (the distance from the susceptor to the inlet), P (operational pressure) and the rate of susceptor rotation to improve the film growth.

High Quality AlGaN Grown on GaN Template with HT-AlN Interlayer

When AlGaN is grown on GaN template, crack networks invariably generate when the thickness of the AlGaN layers over GaN exceeds the critical value. We used thin high temperature deposited AlN layer (HT-AlN) as the interlayer between GaN template and AlGaN epilayer which was very effective in eliminating the cracks in AlGaN epilayer. AlGaN layers with high Al mole fractions were also grown. Characterization showed that the crystalline quality of AlGaN epilayer was fairly good even when the At mole fraction was high.

Monolithic Integration of Light Emitting Diodes, Photodetector and Receiver Circuit in Standard CMOS Technology

A monolithic silicon CMOS optoelectronic integrated circuit (OEIC) is designed and fabricated with standard 0.35 mu m CMOS technology. This OEIC circuit consists of light emitting diodes (LED), silicon dioxide waveguide, photodiodes and receiver circuit. The silicon LED operates in reverse breakdown mode and can be turned on at 8.5V 10mA. The silicon dioxide waveguide is composed of multiple layers of silicon dioxide between different metals layers. A two PN-junctions photodetector composed of n-well/p-substrate junction and p(+) active implantation/n-well junction maximizes the depletion region width. The readout circuitry in pixels is exploited to handle as small as 0.1nA photocurrent. Simulation and testing results show that the optical emissions powers are about two orders higher than the low frequency detectivity of silicon CMOS photodetcctor and receiver circuit.

Combined transparent electrodes for high power GaN-based LEDs with long life time

In this paper fabrication of high power light emitting diodes (LEDs) with combined transparent electrodes on both P-GaN and N-GaN have been demonstrated. Simulation and experimental results show that comparing with traditional metal N electrodes the efficacy of LEDs with transparent N electrode is increased by more than 10% and it is easier in process than the other techniques. Further more, combining the transparent electrodes with dielectric anti-reflection film, the extraction efficiency can be improved by 5%. At the same time, the transparent electrodes were protected by the dielectric film and the reliability of LEDs can be improved.

AlGaN/AlN/GaN/InGaN/GaN DH-HEMTs with improved mobility grown by MOCVD

AlGaN/AlN/GaN/InGaN/GaN double heterojunction high electron mobility transistors (DH-HEMTs) structures with improved buffer isolation have been investigated. The structures were grown by MOCVD on sapphire substrate. AFM result of this structure shows a good surface morphology with the root-mean-square roughness (RMS) of 0.196 nm for a scan area of 5 mu mx5 mu m. A mobility as high as 1950 cm(2)/Vs with the sheet carrier density of 9.89x10(12) cm(-2) was obtained, which was about 50% higher than other results of similar structures which have been reported. Average sheet resistance of 327 Omega/sq was achieved. The HEMTs device using the materials was fabricated, and a maximum drain current density of 718.5 mA/mm, an extrinsic transconductance of 248 mS/mm, a current gain cutoff frequency of 16 GHz and a maximum frequency of oscillation 35 GHz were achieved.

Design of Low Power Multi-Standard Active-RC Filter for WLAN and DVB-H

In this paper, a low-power, highly linear, integrated, active-RC filter exhibiting a multi-standard (IEEE 802.11a/b/g and DVB-H) application and bandwidth (3MHz, 4MHz, 9.5MHz) is present. The filter exploits digitally-controlled polysilicon resister banks and an accurate automatic tuning scheme to account for process and temperature variations. The automatic frequency calibration scheme provides better than 3% corner frequency accuracy. The Butterworth filter is design for receiver (WLAN and DVB-H mode) and transmitter (WLAN mode). The filter dissipation is 3.4 mA in RX mode and 2.3 mA (only for one path) in TX mode from 2.85-V supply. The dissipation of calibration consumes 2mA. The circuit has been fabricated in a 0.35um 47-GHz SiGe BiCMOS technology, the receiver and transmitter occupy 0.28-mm(2) and 0.16-mm(2) (calibration circuit excluded), respectively.

A 5.6-mW Power Dissipation CMOS Frequency Synthesizer for L1/L2 Dual-Band GPS Application

This paper presents a wide tuning range CMOS frequency synthesizer for dual-band GPS receiver, which has been fabricated in a standard 0.18-um RF CMOS process. With a high Q on-chip inductor, the wide-band VCO shows a tuning range from 2 to 3.6GHz to cover 2.45GHz and 3.14GHz in case of process corner or temperature variation, with a current consumption varying accordingly from 0.8mA to 0.4mA, from a 1.8V supply voltage. The measurement results show that the whole frequency synthesizer costs a very low power consumption of 5.6mW working at L I band with in-band phase noise less than -82dBc/Hz and out-of-band phase noise about -112 dBc/Hz at 1MHz offset from a 3.142GHz carrier.

A Complex BPF with On Chip Auto-tuning Architecture for Low-IF Receivers

A 3(rd) order complex band-pass filter (BPF) with auto-tuning architecture is proposed in this paper. It is implemented in 0.18 mu m standard CMOS technology. The complex filter is centered at 4.092MHz with bandwidth of 2.4MHz. The in-band 3(rd) order harmonic input intercept point (IIP3) is larger than 19dBm, with 50 Omega as the source impedance. The input referred noise is about 80 mu V-rms. The RC tuning is based on Binary Search Algorithm (BSA) with tuning accuracy of 3%. The chip area of the tuning system is 0.28x0.22mm(2), less than 1/8 of that of the main-filter which is 0.92x0.59mm(2). After tuning is completed, the tuning system will be turned off automatically to save power and to avoid interference. The complex filter consumes 2.6mA with a 1.8V power supply.

A widely tunable continuous-time LPF for a direct conversion DBS Tuner

A continuous-time 7th-order Butterworth Gm-C low pass filter (LPF) with on-chip automatic tuning circuit has been implemented for a direct conversion DBS tuner in a 0.35um SiGe BiCMOS technology. The filter's -3dB cutoff frequency f(0) can be tuned from 4MHz to 40MHz. A novel translinear transconductor (Gm) cell is used to implement the widely tunable and high linear filter. The filter has -0.5dB passband gain, 28nV/Hz(1/2) input referred noise, -2dBVrms passband IIP3, 24dBVrms stopband IIP3. The I/Q LPFs with the tuning circuit draw 16mA (with f(0)=20MHz) from 3.3 V supply, and occupy an area of 0.45 mm(2).

Neuro-Stimulus Chip with Photodiodes Array for Sub-retinal Implants

A prototype neuro-stimulus chip for sub-retinal implants in blind patients affected by Age-related Macular Degeneration (AMD) or Retinitis Pigmentosa (RP) is presented in this paper. This retinal prosthetic chip was designed to replace the degenerated photoreceptor cells, and in order to stimulate directly the remaining healthy layers of retinal neurons. The current stimulus circuits are monolithic integrated with photodiodes (PD) array, which can convert the illumination on the eyes into bi-phasic electrical pulses. In addition, a novel charge cancellation circuit is used to discharge the electrodes for medical safty. The prototype chip is designed and fabricated in HJTC 0.18 mu m N-well CMOS 1P6M Mix-signal process, with a +/- 2.5 V dual voltage power supply.

A Compact Direct Digital Frequency Synthesizer for System-on-chip

A compact direct digital frequency synthesizer (DDFS) for system-on-chip (SoC) is developed in this paper. For smaller chip size and lower power consumption, the phase to sine mapping data is compressed by using sine symmetry technique, sine-phase difference technique, quad line approximation (QLA) technique and quantization and error read only memory (QE-ROM) technique. The ROM size is reduced by 98 % using the techniques mentioned above. A compact DDFS chip with 32-bit phase storage depth and a 10-bit on-chip digital to analog converter(DAC) has been successfully implemented using standard 0.35um CMOS process. The core area of the DDFS is 1.6mm(2). It consumes 167 mW at 3.3V, and its spurious free dynamic range (SFDR) is 61dB.