Low power pipelined TCAM employing mismatch dependent power allocation technique

This paper presents design of a Low power 256x72 bit TCAM in 0.13um CMOS technology. In contrast to conventional Match line (ML) sensing scheme in which equal power is consumed irrespective of match or mismatch, the ML scheme employed in this design allocates less power to match decisions involving a large number of mismatched bits. Typically, the probability of mismatch is high so this scheme results in significant CAM power reduction. We propose to use this technique along with pipelining of search operation in which the MLs are broken into several segments. Since most words fail to match in first segment, the search operation for subsequent segments is discontinued, resulting in further reduction in power consumption. The above architecture provides 70% power reduction while performing search in 3ns.

Enhancing sensor network lifetime using interactive communication

We are concerned with maximizing the lifetime of a data-gathering wireless sensor network consisting of set of nodes directly communicating with a base-station. We model this scenario as the m-message interactive communication between multiple correlated informants (sensor nodes) and a recipient (base-station). With this framework, we show that m-message interactive communication can indeed enhance network lifetime. Both worst-case and average-case performances are considered.

Eye-view: A retinal image acquisition system

This paper presents a low cost but high resolution retinal image acquisition system of the human eye. The images acquired by a CMOS image sensor are communicated through the Universal Serial Bus (USB) interface to a personal computer for viewing and further processing. The image acquisition time was estimated to be 2.5 seconds. This system can also be used in telemedicine applications.

Interactive Distributed Source Coding in Asymmetric Communication Scenarios

We provide a new unified framework, called "multiple correlated informants - single recipient" communication, to address the variations of the traditional Distributed Source Coding (DSC) problem. Different combinations of the assumptions about the communication scenarios and the objectives of communication result in different variations of the DSC problem. For each of these variations, the complexities of communication and computation of the optimal solution is determined by the combination of the underlying assumptions. In the proposed framework, we address the asymmetric, interactive, and lossless variant of the DSC problem, with various objectives of communication and provide optimal solutions for those. Also, we consider both, the worst-case and average-case scenarios.

Novel window functions for digital filters

Window technique is one of the simplest methods to design Finite Impulse Response (FIR) filters. It uses special functions to truncate an infinite sequence to a finite one. In this paper, we propose window techniques based on integer sequences. The striking feature of the proposed work is that it overcomes all the problems posed by floating point numbers and inaccuracy, as the sequences are made of only integers. Some of these integer window sequences, yield sharp transition, while some of them result in zero ripple in passband and stopband.

Leveraging Partially Enhanced Scan for Improved Observability in Delay Fault Testing

Enhanced Scan design can significantly improve the fault coverage for two pattern delay tests at the cost of exorbitantly high area overhead. The redundant flip-flops introduced in the scan chains have traditionally only been used to launch the two-pattern delay test inputs, not to capture tests results. This paper presents a new, much lower cost partial Enhanced Scan methodology with both improved controllability and observability. Facilitating observation of some hard to observe internal nodes by capturing their response in the already available and underutilized redundant flip-flops improves delay fault coverage with minimal or almost negligible cost. Experimental results on ISCAS'89 benchmark circuits show significant improvement in TDF fault coverage for this new partial enhance scan methodology.

Multi-Tone Testing of Linear and Nonlinear Analog Circuits using Polynomial Coefficients

A method of testing for parametric faults of analog circuits based on a polynomial representation of fault-free function of the circuit is presented. The response of the circuit under test (CUT) is estimated as a polynomial in the applied input voltage at relevant frequencies in addition to DC. Classification or Cur is based on a comparison of the estimated polynomial coefficients with those of the fault free circuit. This testing method requires no design for test hardware as might be added to the circuit fly some other methods. The proposed method is illustrated for a benchmark elliptic filter. It is shown to uncover several parametric faults causing deviations as small as 5% from the nominal values.

Influence of quantum confinement on the photoemission from superlattices of optoelectronic materials

We study the photoemission from quantum wire and quantum dot superlattices with graded interfaces of optoelectronic materials on the basis of newly formulated electron dispersion relations in the presence of external photo-excitation. Besides, the influence of a magnetic field on the photoemission from the aforementioned superlattices together with quantum well superlattices in the presence of a quantizing magnetic field has also been studied in this context. It has been observed taking into account HgTe/Hg1-xCdxTe and InxGa1-xAs/InP that the photoemission from these nanostructures increases with increasing photon energy in quantized steps and exhibits oscillatory dependences with the increase in carrier concentration. Besides, the photoemission decreases with increasing light intensity and wavelength, together with the fact that said emission decreases with increasing thickness exhibiting oscillatory spikes. The strong dependences of the photoemission on the light intensity reflects the direct signature of light waves on the carrier energy spectra. The content of this paper finds six applications in the fields of low dimensional systems in general. (C) 2010 Elsevier Ltd. All rights reserved.

The Photoemission from Quantum Wells, Wires and Carbon Nanotubes:Simplified Theory and Relative Comparison

We investigate the photoemission from quantum wells (QWs) in ultrathin films (UFs) and quantum well wires (QWWs) of non-linear optical materials on the basis of a newly formulated electron dispersion law considering the anisotropies of the effective electron masses, the spin-orbit splitting constants and the presence of the crystal field splitting within the framework of k.p formalism. The results of quantum confined Ill-V compounds form the special cases of our generalized analysis. The photoemission has also been studied for quantum confined II-VI, n-GaP, n-Ge, PtSb2, stressed materials and Bismuth on the basis of respective dispersion relations. It has been found taking quantum confined CdGeAS(2), InAs, InSb, CdS, GaP, Ge, PtSb2, stressed n-InSb and B1 that the photoemission exhibits quantized variations with the incident photon energy, changing electron concentration and film thickness, respectively, for all types of quantum confinement. The photoemission from CNs exhibits oscillatory dependence with increasing normalized electron degeneracy and the signature of the entirely different types of quantum systems are evident from the plots. Besides, under certain special conditions, all the results for all the materials gets simplified to the well-known expression of photoemission from non-degenerate semiconductors and parabolic energy bands, leading to the compatibility test.

Multilevel Dodecagonal Space Vector Generation for Open-end Winding Induction Motor Drive Using Conventional Three Level Inverters

A novel dodecagonal space vector structure for induction motor drive is presented in this paper. It consists of two dodecagons, with the radius of the outer one twice the inner one. Compared to existing dodecagonal space vector structures, to achieve the same PWM output voltage quality, the proposed topology lowers the switching frequency of the inverters and reduces the device ratings to half. At the same time, other benefits obtained from existing dodecagonal space vector structure are retained here. This includes the extension of the linear modulation range and elimination of all 6+/-1 harmonics (n=odd) from the phase voltage. The proposed structure is realized by feeding an open-end winding induction motor with two conventional three level inverters. A detailed calculation of the PWM timings for switching the space vector points is also presented. Simulation and experimental results indicate the possible application of the proposed idea for high power drives.

Reconfigurable Viterbi decoder on mesh connected multiprocessor architecture

In modern wireline and wireless communication systems, Viterbi decoder is one of the most compute intensive and essential elements. Each standard requires a different configuration of Viterbi decoder. Hence there is a need to design a flexible reconfigurable Viterbi decoder to support different configurations on a single platform. In this paper we present a reconfigurable Viterbi decoder which can be reconfigured for standards such as WCDMA, CDMA2000, IEEE 802.11, DAB, DVB, and GSM. Different parameters like code rate, constraint length, polynomials and truncation length can be configured to map any of the above mentioned standards. Our design provides higher throughput and scalable power consumption in various configuration of the reconfigurable Viterbi decoder. The power and throughput can also be optimized for different standards.

Simulation blocks for TOSSIM-T2

We develop several hardware and software simulation blocks for the TinyOS-2 (TOSSIM-T2) simulator. The choice of simulated hardware platform is the popular MICA2 mote. While the hardware simulation elements comprise of radio and external flash memory, the software blocks include an environment noise model, packet delivery model and an energy estimator block for the complete system. The hardware radio block uses the software environment noise model to sample the noise floor. The packet delivery model is built by establishing the SNR-PRR curve for the MICA2 system. The energy estimator block models energy consumption by Micro Controller Unit(MCU), Radio, LEDs, and external flash memory. Using the manufacturerpsilas data sheets we provide an estimate of the energy consumed by the hardware during transmission, reception and also track several of the MCUs states with the associated energy consumption. To study the effectiveness of this work, we take a case study of a paper presented in [1]. We obtain three sets of results for energy consumption through mathematical analysis, simulation using the blocks built into PowerTossim-T2 and finally laboratory measurements. Since there is a significant match between these result sets, we propose our blocks for T2 community to effectively test their application energy requirements and node life times.

Modeling and Analysis of Noise Margin in SET Logic

In this paper the static noise margin for SET (single electron transistor) logic is defined and compact models for the noise margin are developed by making use of the MIB (Mahapatra-Ionescu-Banerjee) model. The variation of the noise margin with temperature and background charge is also studied. A chain of SET inverters is simulated to validate the definition of various logic levels (like VIH, VOH, etc.) and noise margin. Finally the noise immunity of SET logic is compared with current CMOS logic.

Three-level inverter fed open-end winding IM drive with common mode voltage elimination and reduced power device count

A three-level space phasor generation scheme with common mode elimination and with reduced power device count is proposed for an open end winding induction motor in this paper. The open end winding induction motor is fed by the three-level inverters from both sides. Each two level inverter is formed by cascading two two-level inverters. By sharing the bottom inverter for the two three-level inverters on either side, the power device count is reduced. The switching states with zero common mode voltage variation are selected for PWM switching so that there is no alternating common mode voltage in the pole voltages as well as in phase voltages. Only two isolated DC-links, with half the voltage rating of a conventional three-level neutral point clamped inverter, are needed for the proposed scheme.

Formal Verification of Full-Wave Rectifier: A Case Study

We present a case study of formal verification of full-wave rectifier for analog and mixed signal designs. We have used the Checkmate tool from CMU [1], which is a public domain formal verification tool for hybrid systems. Due to the restriction imposed by Checkmate it necessitates to make the changes in the Checkmate implementation to implement the complex and non-linear system. Full-wave rectifier has been implemented by using the Checkmate custom blocks and the Simulink blocks from MATLAB from Math works. After establishing the required changes in the Checkmate implementation we are able to efficiently verify, the safety properties of the full-wave rectifier.