Leveraging Partially Enhanced Scan for Improved Observability in Delay Fault Testing


Autoria(s): Deepak, KG; Reyna, Robinson; Singh, Virendra; Singh, Adit D
Data(s)

2009

Resumo

Enhanced Scan design can significantly improve the fault coverage for two pattern delay tests at the cost of exorbitantly high area overhead. The redundant flip-flops introduced in the scan chains have traditionally only been used to launch the two-pattern delay test inputs, not to capture tests results. This paper presents a new, much lower cost partial Enhanced Scan methodology with both improved controllability and observability. Facilitating observation of some hard to observe internal nodes by capturing their response in the already available and underutilized redundant flip-flops improves delay fault coverage with minimal or almost negligible cost. Experimental results on ISCAS'89 benchmark circuits show significant improvement in TDF fault coverage for this new partial enhance scan methodology.

Formato

application/pdf

Identificador

http://eprints.iisc.ernet.in/26560/1/getPDF.pdf_4.pdf

Deepak, KG and Reyna, Robinson and Singh, Virendra and Singh, Adit D (2009) Leveraging Partially Enhanced Scan for Improved Observability in Delay Fault Testing. In: 18th Asian Test Symposium, NOV 23-26, 2009, Taichung.

Publicador

IEEE

Relação

http://ieeexplore.ieee.org/search/srchabstract.jsp?tp=&arnumber=5359346&queryText%3D%28leveraging+partially+enhanced+scan+for+improved+observability+in+delay+fault+testing%29%26openedRefinements%3D*&tag=1

http://eprints.iisc.ernet.in/26560/

Palavras-Chave #Electronic Systems Engineering (Formerly, (CEDT) Centre for Electronic Design & Technology) #Supercomputer Education & Research Centre
Tipo

Conference Paper

PeerReviewed