Caracterização elétrica de túnel-FET em estrutura de nanofio com fontes de SiGe e Ge em função da temperatura.

Este trabalho teve como objetivo estudar os transistores de tunelamento por efeito de campo em estruturas de nanofio (NW-TFET), sendo realizado através de analises com base em explicações teóricas, simulações numéricas e medidas experimentais. A fim de avaliar melhorar o desempenho do NW-TFET, este trabalho utilizou dispositivos com diferentes materiais de fonte, sendo eles: Si, liga SiGe e Ge, além da variação da espessura de HfO2 no material do dielétrico de porta. Com o auxílio de simulações numéricas foram obtidos os diagramas de bandas de energia dos dispositivos NW-TFET com fonte de Si0,73Ge0,27 e foi analisada a influência de cada um dos mecanismos de transporte de portadores para diversas condições de polarização, sendo observado a predominância da influência da recombinação e geração Shockley-Read-Hall (SRH) na corrente de desligamento, do tunelamento induzido por armadilhas (TAT) para baixos valores de tensões de porta (0,5V > VGS > 1,5V) e do tunelamento direto de banda para banda (BTBT) para maiores valores tensões de porta (VGS > 1,5V). A predominância de cada um desses mecanismos de transporte foi posteriormente comprovada com a utilização do método de Arrhenius, sendo este método adotado em todas as análises do trabalho. O comportamento relativamente constante da corrente dos NW-TFETs com a temperatura na região de BTBT tem chamado a atenção e por isso foi realizado o estudo dos parâmetros analógicos em função da temperatura. Este estudo foi realizado comparando a influência dos diferentes materiais de fonte. O uso de Ge na fonte, permitiu a melhora na corrente de tunelamento, devido à sua menor banda proibida, aumentando a corrente de funcionamento (ION) e a transcondutância do dispositivo. Porém, devido à forte dependência de BTBT com o campo elétrico, o uso de Ge na fonte resulta em uma maior degradação da condutância de saída. Entretanto, a redução da espessura de HfO2 no dielétrico de porta resultou no melhor acoplamento eletrostático, também aumentando a corrente de tunelamento, fazendo com que o dispositivo com fonte Ge e menor HfO2 apresentasse melhores resultados analógicos quando comparado ao puramente de Si. O uso de diferentes materiais durante o processo de fabricação induz ao aumento de defeitos nas interfaces do dispositivo. Ao longo deste trabalho foi realizado o estudo da influência da densidade de armadilhas de interface na corrente do dispositivo, demonstrando uma relação direta com o TAT e a formação de uma região de platô nas curvas de IDS x VGS, além de uma forte dependência com a temperatura, aumentando a degradação da corrente para temperaturas mais altas. Além disso, o uso de Ge introduziu maior número de impurezas no óxido, e através do estudo de ruído foi observado que o aumento na densidade de armadilhas no óxido resultou no aumento do ruído flicker em baixa frequência, que para o TFET, ocorre devido ao armadilhamento e desarmadilhamento de elétrons na região do óxido. E mais uma vez, o melhor acoplamento eletrostático devido a redução da espessura de HfO2, resultou na redução desse ruído tornando-se melhor quando comparado à um TFET puramente de Si. Neste trabalho foi proposto um modelo de ruído em baixa frequência para o NW-TFET baseado no modelo para MOSFET. Foram realizadas apenas algumas modificações, e assim, obtendo uma boa concordância com os resultados experimentais na região onde o BTBT é o mecanismo de condução predominante.

Morphology Change of C60 Islands on Organic Crystals Observed by Atomic Force Microscopy

Organic-organic heterojunctions are nowadays highly regarded materials for light-emitting diodes, field-effect transistors, and photovoltaic cells with the prospect of designing low-cost, flexible, and efficient electronic devices.1-3 However, the key parameter of optimized heterojunctions relies on the choice of the molecular compounds as well as on the morphology of the organic-organic interface,4 which thus requires fundamental studies. In this work, we investigated the deposition of C60 molecules at room temperature on an organic layer compound, the salt bis(benzylammonium)bis(oxalato)cupurate(II), by means of noncontact atomic force microscopy. Three-dimensional molecular islands of C60 having either triangular or hexagonal shapes are formed on the substrate following a "Volmer-Weber" type of growth. We demonstrate the dynamical reshaping of those C60 nanostructures under the local action of the AFM tip at room temperature. The dissipated energy is about 75 meV and can be interpreted as the activation energy required for this migration process.

Controlling Long-Range Ordered Self-assembly of Solid-Binding Peptide Monolayers on Atomically Flat Layered Materials

Thesis (Master's)--University of Washington, 2016-06

Controlled growth of carbon nanotubes for high performance nanoelectronics

Unique electrical and mechanical properties of single-walled carbon nanotubes (SWNTs) have made them one of the most promising candidates for next-generation nanoelectronics. Efficient utilization of the exceptional properties of SWNTs requires controlling their growth direction (e.g., vertical, horizontal) and morphologies (e.g., straight, junction, coiled). ^ In this dissertation, the catalytic effect on the branching of SWNTs, Y-shaped SWNTs (Y-SWNTs), was investigated. The formation of Y-shaped branches was found to be dependent on the composition of the catalysts. Easier carbide formers have a strong tendency to attach to the sidewall of SWNTs and thus enhance the degree of branching. Y-SWNTs based field-effect transistors (FETs) were fabricated and modulated by the metallic branch of the Y-SWNTs, exhibiting ambipolar characteristics at room temperature. A subthreshold swing of 700 mV/decade and an on/off ratio of 105 with a low off-state current of 10-13 A were obtained. The transport phenomena associated with Y- and cross-junction configurations reveals that the conduction mechanism in the SWNT junctions is governed by thermionic emission at T > 100 K and by tunneling at T < 100 K. ^ Furthermore, horizontally aligned SWNTs were synthesized by the controlled modification of external fields and forces. High performance carbon nanotube FETs and logic circuit were demonstrated utilizing the aligned SWNTs. It is found that the hysteresis in CNTFETs can be eliminated by removing absorbed water molecules on the CNT/SiO2 interface by vacuum annealing, hydrophobic surface treatment, and surface passivation. SWNT “serpentines” were synthesized by utilization of the interaction between drag force from gas flow and Van der Waals force with substrates. The curvature of bent SWNTs could be tailored by adjusting the gas flow rate, and changing the gas flow direction with respect to the step-edges on a single-crystal quartz substrate. Resistivity of bent SWNTs was observed to increase with curvature, which can be attributed to local deformations and possible chirality shift at curved part. ^ Our results show the successful synthesis of SWNTs having controllable morphologies and directionality. The capability of tailoring the electrical properties of SWNTs makes it possible to build an all-nanotube device by integrating SWNTs, having different functionalities, into complex circuits. ^

Enhanced zinc oxide and graphene nanostructures for electronics and sensing applications

Zinc oxide and graphene nanostructures are important technological materials because of their unique properties and potential applications in future generation of electronic and sensing devices. This dissertation investigates a brief account of the strategies to grow zinc oxide nanostructures (thin film and nanowire) and graphene, and their applications as enhanced field effect transistors, chemical sensors and transparent flexible electrodes. Nanostructured zinc oxide (ZnO) and low-gallium doped zinc oxide (GZO) thin films were synthesized by a magnetron sputtering process. Zinc oxide nanowires (ZNWs) were grown by a chemical vapor deposition method. Field effect transistors (FETs) of ZnO and GZO thin films and ZNWs were fabricated by standard photo and electron beam lithography processes. Electrical characteristics of these devices were investigated by nondestructive surface cleaning, ultraviolet irradiation treatment at high temperature and under vacuum. GZO thin film transistors showed a mobility of ∼5.7 cm2/V·s at low operation voltage of <5 V and a low turn-on voltage of ∼0.5 V with a sub threshold swing of ∼85 mV/decade. Bottom gated FET fabricated from ZNWs exhibit a very high on-to-off ratio (∼106) and mobility (∼28 cm2/V·s). A bottom gated FET showed large hysteresis of ∼5.0 to 8.0 V which was significantly reduced to ∼1.0 V by the surface treatment process. The results demonstrate charge transport in ZnO nanostructures strongly depends on its surface environmental conditions and can be explained by formation of depletion layer at the surface by various surface states. A nitric oxide (NO) gas sensor using single ZNW, functionalized with Cr nanoparticles was developed. The sensor exhibited average sensitivity of ∼46% and a minimum detection limit of ∼1.5 ppm for NO gas. The sensor also is selective towards NO gas as demonstrated by a cross sensitivity test with N2, CO and CO2 gases. Graphene film on copper foil was synthesized by chemical vapor deposition method. A hot press lamination process was developed for transferring graphene film to flexible polymer substrate. The graphene/polymer film exhibited a high quality, flexible transparent conductive structure with unique electrical-mechanical properties; ∼88.80% light transmittance and ∼1.1742Ω/sq k sheet resistance. The application of a graphene/polymer film as a flexible and transparent electrode for field emission displays was demonstrated.

Investigation of generation -recombination noise and related processes in aluminum gallium arsenide TEGFETs and Hall structures with quantum wells

Experimental and theoretical studies regarding noise processes in various kinds of AlGaAs/GaAs heterostructures with a quantum well are reported. The measurement processes, involving a Fast Fourier Transform and analog wave analyzer in the frequency range from 10 Hz to 1 MHz, a computerized data storage and processing system, and cryostat in the temperature range from 78 K to 300 K are described in detail. The current noise spectra are obtained with the “three-point method”, using a Quan-Tech and avalanche noise source for calibration. ^ The properties of both GaAs and AlGaAs materials and field effect transistors, based on the two-dimensional electron gas in the interface quantum well, are discussed. Extensive measurements are performed in three types of heterostructures, viz., Hall structures with a large spacer layer, modulation-doped non-gated FETs, and more standard gated FETs; all structures are grown by MBE techniques. ^ The Hall structures show Lorentzian generation-recombination noise spectra with near temperature independent relaxation times. This noise is attributed to g-r processes in the 2D electron gas. For the TEGFET structures, we observe several Lorentzian g-r noise components which have strongly temperature dependent relaxation times. This noise is attributed to trapping processes in the doped AlGaAs layer. The trap level energies are determined from an Arrhenius plot of log (τT2) versus 1/T as well as from the plateau values. The theory to interpret these measurements and to extract the defect level data is reviewed and further developed. Good agreement with the data is found for all reported devices. ^

Noise in gallium nitride-based quantum well structures used for nanometer devices in the frequency range 1 Hz--3 Mhz and temperature range 77K--324K

Electronic noise has been investigated in AlxGa1−x N/GaN Modulation-Doped Field Effect Transistors (MODFETs) of submicron dimensions, grown for us by MBE (Molecular Beam Epitaxy) techniques at Virginia Commonwealth University by Dr. H. Morkoç and coworkers. Some 20 devices were grown on a GaN substrate, four of which have leads bonded to source (S), drain (D), and gate (G) pads, respectively. Conduction takes place in the quasi-2D layer of the junction (xy plane) which is perpendicular to the quantum well (z-direction) of average triangular width ∼3 nm. A non-doped intrinsic buffer layer of ∼5 nm separates the Si-doped donors in the AlxGa1−xN layer from the 2D-transistor plane, which affords a very high electron mobility, thus enabling high-speed devices. Since all contacts (S, D, and G) must reach through the AlxGa1−xN layer to connect internally to the 2D plane, parallel conduction through this layer is a feature of all modulation-doped devices. While the shunting effect may account for no more than a few percent of the current IDS, it is responsible for most excess noise, over and above thermal noise of the device. ^ The excess noise has been analyzed as a sum of Lorentzian spectra and 1/f noise. The Lorentzian noise has been ascribed to trapping of the carriers in the AlxGa1−xN layer. A detailed, multitrapping generation-recombination noise theory is presented, which shows that an exponential relationship exists for the time constants obtained from the spectral components as a function of 1/kT. The trap depths have been obtained from Arrhenius plots of log (τT2) vs. 1000/T. Comparison with previous noise results for GaAs devices shows that: (a) many more trapping levels are present in these nitride-based devices; (b) the traps are deeper (farther below the conduction band) than for GaAs. Furthermore, the magnitude of the noise is strongly dependent on the level of depletion of the AlxGa1−xN donor layer, which can be altered by a negative or positive gate bias VGS. ^ Altogether, these frontier nitride-based devices are promising for bluish light optoelectronic devices and lasers; however, the noise, though well understood, indicates that the purity of the constituent layers should be greatly improved for future technological applications. ^

Effects of alternating current voltage amplitude and oxide capacitance on mid-gap interface state defect density extractions in In0.53Ga 0.47As capacitors

This work looks at the effect on mid-gap interface state defect density estimates for In0.53Ga0.47As semiconductor capacitors when different AC voltage amplitudes are selected for a fixed voltage bias step size (100 mV) during room temperature only electrical characterization. Results are presented for Au/Ni/Al2O3/In0.53Ga0.47As/InP metal–oxide–semiconductor capacitors with (1) n-type and p-type semiconductors, (2) different Al2O3 thicknesses, (3) different In0.53Ga0.47As surface passivation concentrations of ammonium sulphide, and (4) different transfer times to the atomic layer deposition chamber after passivation treatment on the semiconductor surface—thereby demonstrating a cross-section of device characteristics. The authors set out to determine the importance of the AC voltage amplitude selection on the interface state defect density extractions and whether this selection has a combined effect with the oxide capacitance. These capacitors are prototypical of the type of gate oxide material stacks that could form equivalent metal–oxide–semiconductor field-effect transistors beyond the 32 nm technology node. The authors do not attempt to achieve the best scaled equivalent oxide thickness in this work, as our focus is on accurately extracting device properties that will allow the investigation and reduction of interface state defect densities at the high-k/III–V semiconductor interface. The operating voltage for future devices will be reduced, potentially leading to an associated reduction in the AC voltage amplitude, which will force a decrease in the signal-to-noise ratio of electrical responses and could therefore result in less accurate impedance measurements. A concern thus arises regarding the accuracy of the electrical property extractions using such impedance measurements for future devices, particularly in relation to the mid-gap interface state defect density estimated from the conductance method and from the combined high–low frequency capacitance–voltage method. The authors apply a fixed voltage step of 100 mV for all voltage sweep measurements at each AC frequency. Each of these measurements is repeated 15 times for the equidistant AC voltage amplitudes between 10 mV and 150 mV. This provides the desired AC voltage amplitude to step size ratios from 1:10 to 3:2. Our results indicate that, although the selection of the oxide capacitance is important both to the success and accuracy of the extraction method, the mid-gap interface state defect density extractions are not overly sensitive to the AC voltage amplitude employed regardless of what oxide capacitance is used in the extractions, particularly in the range from 50% below the voltage sweep step size to 50% above it. Therefore, the use of larger AC voltage amplitudes in this range to achieve a better signal-to-noise ratio during impedance measurements for future low operating voltage devices will not distort the extracted interface state defect density.

Organic functionalisation, doping and characterisation of semiconductor surfaces for future CMOS device applications

Organic Functionalisation, Doping and Characterisation of Semiconductor Surfaces for Future CMOS Device Applications Semiconductor materials have long been the driving force for the advancement of technology since their inception in the mid-20th century. Traditionally, micro-electronic devices based upon these materials have scaled down in size and doubled in transistor density in accordance with the well-known Moore’s law, enabling consumer products with outstanding computational power at lower costs and with smaller footprints. According to the International Technology Roadmap for Semiconductors (ITRS), the scaling of metal-oxide-semiconductor field-effect transistors (MOSFETs) is proceeding at a rapid pace and will reach sub-10 nm dimensions in the coming years. This scaling presents many challenges, not only in terms of metrology but also in terms of the material preparation especially with respect to doping, leading to the moniker “More-than-Moore”. Current transistor technologies are based on the use of semiconductor junctions formed by the introduction of dopant atoms into the material using various methodologies and at device sizes below 10 nm, high concentration gradients become a necessity. Doping, the controlled and purposeful addition of impurities to a semiconductor, is one of the most important steps in the material preparation with uniform and confined doping to form ultra-shallow junctions at source and drain extension regions being one of the key enablers for the continued scaling of devices. Monolayer doping has shown promise to satisfy the need to conformally dope at such small feature sizes. Monolayer doping (MLD) has been shown to satisfy the requirements for extended defect-free, conformal and controllable doping on many materials ranging from the traditional silicon and germanium devices to emerging replacement materials such as III-V compounds This thesis aims to investigate the potential of monolayer doping to complement or replace conventional doping technologies currently in use in CMOS fabrication facilities across the world.

Few-layer, large-area, 2D covalent organic framework semiconductor thin films.

In this work, we synthesize large-area thin films of a conjugated, imine-based, two-dimensional covalent organic framework at the solution/air interface. Thicknesses between ∼2-200 nm are achieved. Films can be transferred to any desired substrate by lifting from underneath, enabling their use as the semiconducting active layer in field-effect transistors.

Epitaxial growth of molecular crystals on van der Waals substrates for high-performance organic electronics

Epitaxial van der Waals (vdW) heterostructures of organic and layered materials are demonstrated to create high-performance organic electronic devices. High-quality rubrene films with large single-crystalline domains are grown on h-BN dielectric layers via vdW epitaxy. In addition, high carrier mobility comparable to free-standing single-crystal counterparts is achieved by forming interfacial electrical contacts with graphene electrodes.

Development of functionalised multiwalled carbon nanotube/polyaniline composites for electrical applications

Combining intrinsically conducting polymers with carbon nanotubes (CNT) helps in creating composites with superior electrical and thermal characteristics. These composites are capable of replacing metals and semiconductors as they possess unique combination of electrical conductivity, flexibility, stretchability, softness and bio-compatibility. Their potential for use in various organic devices such as super capacitors, printable conductors, optoelectronic devices, sensors, actuators, electrochemical devices, electromagnetic interference shielding, field effect transistors, LEDs, thermoelectrics etc. makes them excellent substitutes for present day semiconductors.However, many of these potential applications have not been fully exploited because of various open–ended challenges. Composites meant for use in organic devices require highly stable conductivity for the longevity of the devices. CNT when incorporated at specific proportions, and with special methods contributes quite positively to this end.The increasing demand for energy and depleting fossil fuel reserves has broadened the scope for research into alternative energy sources. A unique and efficient method for harnessing energy is thermoelectric energy conversion method. Here, heat is converted directly into electricity using a class of materials known as thermoelectric materials. Though polymers have low electrical conductivity and thermo power, their low thermal conductivity favours use as a thermoelectric material. The thermally disconnected, but electrically connected carrier pathways in CNT/Polymer composites can satisfy the so-called “phonon-glass/electron-crystal” property required for thermoelectric materials. Strain sensing is commonly used for monitoring in engineering, medicine, space or ocean research. Polymeric composites are ideal candidates for the manufacture of strain sensors. Conducting elastomeric composites containing CNT are widely used for this application. These CNT/Polymer composites offer resistance change over a large strain range due to the low Young‟s modulus and higher elasticity. They are also capable of covering surfaces with arbitrary curvatures.Due to the high operating frequency and bandwidth of electronic equipments electromagnetic interference (EMI) has attained the tag of an „environmental pollutant‟, affecting other electronic devices as well as living organisms. Among the EMI shielding materials, polymer composites based on carbon nanotubes show great promise. High strength and stiffness, extremely high aspect ratio, and good electrical conductivity of CNT make it a filler of choice for shielding applications. A method for better dispersion, orientation and connectivity of the CNT in polymer matrix is required to enhance conductivity and EMI shielding. This thesis presents a detailed study on the synthesis of functionalised multiwalled carbon nanotube/polyaniline composites and their application in electronic devices. The major areas focused include DC conductivity retention at high temperature, thermoelectric, strain sensing and electromagnetic interference shielding properties, thermogravimetric, dynamic mechanical and tensile analysis in addition to structural and morphological studies.

Développement de la polymérisation par (hétéro)arylation directe pour l’électronique organique

L’électronique organique suscite un intérêt grandissant en recherche grâce aux nouvelles possibilités qu’elle offre pour faciliter l’intégration de dispositifs électroniques dans nos vies. Grâce à elle, il est possible d’envisager des produits légers, flexibles et peu coûteux à produire. Les classes majeures de dispositifs étudiées sont les cellules photovoltaïques organiques (CPO) et les transistors organiques à effet de champ (TOEC). Dans les dernières années, une attention particulière a été portée sur les méthodes de polymérisation des matériaux organiques entrant dans la fabrication de ces dispositifs. La polymérisation par (hétéro)arylation directe (PHAD) catalysée au Pd offre une synthèse sans dérivé organométallique utilisant simplement un lien C-H aromatique, ce qui facilite la purification, diminue le nombre d’étapes et rend possible la production de matériaux à plus faible coût. De plus, la PHAD permet la préparation de matériaux qui était difficile, voire impossible, à obtenir auparavant. Cependant, l’inconvénient majeur de la PHAD reste sa limitation à certaines classes de polymères possédant des monomères ayant des positions bloquées favorisant qu’une seule paire de liaisons C-H. Dans le cadre de ces travaux de doctorat, l’objectif général est d’étudier la polymérisation par PHAD afin d’accéder à des classes de monomères qui n’étaient pas envisageables auparavant et à étendre l’application de cet outil dans le domaine des polymères conjugués. Plus spécifiquement, nous avons étudié l’utilisation de groupements protecteurs et partants sur des unités de benzodithiophènes et de bithiophène-silylés. Suivant ces résultats, nos travaux ont porté sur la polymérisation de dérivés de bithiophènes avec des bromo(aryle)s, une classe de polymères fréquemment utilisée en électronique organique mais qui était jugée impossible à polymériser par PHAD auparavant. Cette étude a montré l’importance de contrôler la PHAD afin d’obtenir le polymère souhaité. Finalement, nous avons étudié l’effet du système catalytique sur le taux de β−ramifications lors de la synthèse de polymères à base de thiophènes. Dans cette dernière étude, nous avons démontré l’importance d’utiliser des outils de caractérisation adéquats afin de confirmer la qualité des polymères obtenus.