KDP/PEDOT: PSS mixture as a new alternative in the fabrication of pressure sensing devices

In this work we studied the mixture of poly(3,4-ethylenedioxythiophene): poly(styrenesulfonate) (PEDOT:PSS), a commercial polymer, with monobasic potassium phosphate (KDP), a piezoelectric salt, as a possible novel material in the fabrication of a low cost, easy-to-make,flexible pressure sensing device. The mixture between KDP and PEDOT: PSS was painted in a flexible polyester substrate and dried. Afterwards, I x V curves were carried out. The samples containing KDP presented higher values of current in smaller voltages than the PEDOT: PSS without KDP. This can mean a change in the chain arrays. Other results showed that the material responds to directly applied pressure to the sample that can be useful to sensors fabrication. (c) 2008 Elsevier B.V. All rights reserved.

Design, development, and testing of X-band amplifying reflectarrays

The design and development of two X-band amplifying reflectarrays is presented. The arrays use dual-polarized aperture coupled patch antennas with FET transistors and phasing circuits to amplify a microwave signal and to radiate it in a chosen direction. Two cases are considered, one when a reflectarray converts a spherical wave due to a feed horn into a plane wave radiated into a boresight direction, and two, when the reflectarray converts a spherical wave due to a dual-polarized four-element feed array into a co-focal spherical wave. This amplified signal is received in an orthogonal port of the feed array so that the entire structure acts as a spatial power combiner. The two amplifying arrays are tested in the near-field zone for phase distribution over their apertures to achieve the required beam formation. Alternatively, their radiation patterns or gains are investigated.

Photo-induced instability of nanocrystalline silicon TFTs

We examine the instability behavior of nanocrystalline silicon (nc-Si) thin-film transistors (TFTs) in the presence of electrical and optical stress. The change in threshold voltage and sub-threshold slope is more significant under combined bias-and-light stress when compared to bias stress alone. The threshold voltage shift (Delta V-T) after 6 h of bias stress is about 7 times larger in the case with illumination than in the dark. Under bias stress alone, the primary instability mechanism is charge trapping at the semiconductor/insulator interface. In contrast, under combined bias-and-light stress, the prevailing mechanism appears to be the creation of defect states in the channel, and believed to take place in the amorphous phase, where the increase in the electron density induced by electrical bias enhances the non-radiative recombination of photo-excited electron-hole pairs. The results reported here are consistent with observations of photo-induced efficiency degradation in solar cells.

Solid-state Marx based two-switch voltage modulator for the On-Line Isotope Mass Separator accelerator at the European Organization for Nuclear Research

A new circuit topology is proposed to replace the actual pulse transformer and thyratron based resonant modulator that supplies the 60 kV target potential for the ion acceleration of the On-Line Isotope Mass Separator accelerator, the stability of which is critical for the mass resolution downstream separator, at the European Organization for Nuclear Research. The improved modulator uses two solid-state switches working together, each one based on the Marx generator concept, operating as series and parallel switches, reducing the stress on the series stacked semiconductors, and also as auxiliary pulse generator in order to fulfill the target requirements. Preliminary results of a 10 kV prototype, using 1200 V insulated gate bipolar transistors and capacitors in the solid-state Marx circuits, ten stages each, with an electrical equivalent circuit of the target, are presented, demonstrating both the improved voltage stability and pulse flexibility potential wanted for this new modulator.

Phototransistor with nanocrystalline Si/amorphous Si bilayer channel

We report a field-effect phototransistor with a channel comprising a thin nanocrystalline silicon transport layer and a thicker hydrogenated amorphous silicon absorption layer. The semiconductor and dielectric layers were deposited by radio-frequency plasma enhanced chemical vapor deposition. The phototransistor with channel length of 24 microns and photosensitive area of 1.4 mm(2) shows an off-current of about 1 pA, and high photoconductive gain in the subthreshold region. Measurements of the quantum efficiency at different incident light intensities and biasing conditions, along with spectral-response characteristics, and threshold voltage stability characterization demonstrate the feasibility of the phototransistor for low light level detection.

Projecto de um conversor redutor CC-CC comutado para SoC

A evolução da tecnologia CMOS tem possibilitado uma maior densidade de integração de circuitos tornando possível o aumento da complexidade dos sistemas. No entanto, a integração de circuitos de gestão de potência continua ainda em estudo devido à dificuldade de integrar todos os componentes. Esta solução apresenta elevadas vantagens, especialmente em aplicações electrónicas portáteis alimentadas a baterias, onde a autonomia é das principais características. No âmbito dos conversores redutores existem várias topologias de circuitos que são estudadas na área de integração. Na categoria dos conversores lineares utiliza-se o LDO (Low Dropout Regulator), apresentando no entanto baixa eficiência para relações de conversão elevadas. Os conversores comutados são elaborados através do recurso a circuitos de comutação abrupta, em que a eficiência deste tipo de conversores não depende do rácio de transformação entre a tensão de entrada e a de saída. A diminuição física dos processos CMOS tem como consequência a redução da tensão máxima que os transístores suportam, impondo o estudo de soluções tolerantes a “altatensão”, com o intuito de manter compatibilidade com tensões superiores que existam na placa onde o circuito é incluído. Os sistemas de gestão de energia são os primeiros a acompanhar esta evolução, tendo de estar aptos a fornecer a tensão que os restantes circuitos requerem. Neste trabalho é abordada uma metodologia de projecto para conversores redutores CCCC comutados em tecnologia CMOS, tendo-se maximizado a frequência com vista à integração dos componentes de filtragem em circuito integrado. A metodologia incide sobre a optimização das perdas totais inerentes à comutação e condução, dos transístores de potência e respectivos circuitos auxiliares. É apresentada uma nova metodologia para o desenvolvimento de conversores tolerantes a “alta-tensão”.

A Step-up mu-Power Converter for Solar Energy Harvesting Applications, using Hill Climbing Maximum Power Point Tracking

This paper presents a step-up micro-power converter for solar energy harvesting applications. The circuit uses a SC voltage tripler architecture, controlled by an MPPT circuit based on the Hill Climbing algorithm. This circuit was designed in a 0.13 mu m CMOS technology in order to work with an a-Si PV cell. The circuit has a local power supply voltage, created using a scaled down SC voltage tripler, controlled by the same MPPT circuit, to make the circuit robust to load and illumination variations. The SC circuits use a combination of PMOS and NMOS transistors to reduce the occupied area. A charge re-use scheme is used to compensate the large parasitic capacitors associated to the MOS transistors. The simulation results show that the circuit can deliver a power of 1266 mu W to the load using 1712 mu W of power from the PV cell, corresponding to an efficiency as high as 73.91%. The simulations also show that the circuit is capable of starting up with only 19% of the maximum illumination level.

Membrane selectivity versus sensor response in hydrogenated amorphous silicon CHEMFETs using a semi-empirical model

Toxic amides, such as acrylamide, are potentially harmful to Human health, so there is great interest in the fabrication of compact and economical devices to measure their concentration in food products and effluents. The CHEmically Modified Field Effect Transistor (CHEMFET) based onamorphous silicon technology is a candidate for this type of application due to its low fabrication cost. In this article we have used a semi-empirical modelof the device to predict its performance in a solution of interfering ions. The actual semiconductor unit of the sensor was fabricated by the PECVD technique in the top gate configuration. The CHEMFET simulation was performed based on the experimental current voltage curves of the semiconductor unit and on an empirical model of the polymeric membrane. Results presented here are useful for selection and design of CHEMFET membranes and provide an idea of the limitations of the amorphous CHEMFET device. In addition to the economical advantage, the small size of this prototype means it is appropriate for in situ operation and integration in a sensor array.

Produção e caracterização de silício policristalino e sua aplicação a TFTS

Dissertação para obtenção do Grau de Doutor em Engenharia dos Materiais, especialidade Microelectrónica e Optoelectrónica, pela Universidade Nova de Lisboa, Faculdade de Ciências e Tecnologia

Solid-State bipolar Marx modulator modeling

A mathematical model that simulates the operation of a solid-state bipolar Marx modulator topology, including the influence of parasitic capacitances is presented and discussed as a tool to analyze the circuit behavior and to assist the design engineer to select the semiconductor components and to enhance the operating performance. Simulations show good agreement with experimental results, considering a four stage circuit assembled with 1200 V isolated gate bipolar transistors and diodes, operating at 1000 V dc input voltage and 1-kHz frequency, giving 4 kV and 10-mu s output pulses into several resistive loads. Results show that parasitic capacitances between Marx cells to ground can significantly load the solid-state switches, adding new operating circuit conditions.

Marx-Type solid-state bipolar modulator topologies: Performance comparison

The operation of generalized Marx-type solid-state bipolar modulators is discussed and compared with simplified Marx-derived circuits, to evaluate their capability to deal with various load conditions. A comparative analysis on the number of switches per cell, fiber optic trigger count, losses, and switch hold-off voltages has been made. A circuit topology is obtained as a compromise in terms of operating performance, trigger simplicity, and switching losses. A five-stage laboratory prototype of this circuit has been assembled using 1200 V insulated gate bipolar transistors (IGBTs) and diodes, operating with 1000 V dc input voltage and 1 kHz frequency, giving 5 kV bipolar pulses, with 2.5 mu s pulse width and 5 mu s relaxation time into resistive, capacitive, and inductive loads.

Fully transparent ZnO thin-film transistor produced at room temperature

Advanced Materials, Vol. 17, nº 5

Construção de um variador de frequência

A dificuldade de controlo de um motor de indução, bem como o armazenamento de energia CC e posterior utilização como energia alternada promoveram o desenvolvimento de variadores de frequência e inversores. Assim, como projeto de tese de mestrado em Automação e Sistemas surge o desenvolvimento de um variador de frequência. Para elaboração do variador de frequência efetuou-se um estudo sobre as técnicas de modulação utilizadas nos inversores. A técnica escolhida e utilizada é a Sinusoidal Pulse Width Modulation (SPWM). Esta técnica baseia-se na modelação por largura de impulso (PWM), o qual é formado por comparação de um sinal de referência com um sinal de portadora de elevada frequência. Por sua vez, a topologia escolhida para o inversor corresponde a um Voltage Source Inverter (VSI) de ponte trifásica completa a três terminais. O desenvolvimento da técnica de modulação SPWM levou ao desenvolvimento de um modelo de simulação em SIMULINK, o qual permitiu retirar conclusões sobre os resultados obtidos. Na fase de implementação, foram desenvolvidas placas para o funcionamento do variador de frequência. Assim, numa fase inicial foi desenvolvida a placa de controlo, a qual contém a unidade de processamento e que é responsável pela atuação de Insulated Gate Bipolar Transistors (IGBTs). Para além disso, foi desenvolvida uma placa para proteção dos IGBTs (evitando condução simultânea no mesmo terminal) e uma placa de fontes isoladas para alimentação dos circuitos e para atuação dos IGBTs. Ainda, foi desenvolvida a técnica de SPWM em software para a unidade de controlo e finalmente foi desenvolvida uma interface gráfica para interação com o utilizador. A validação do projeto foi conseguida através da variação da velocidade do motor de indução trifásico. Para isso, este foi colocado a funcionar a diversas frequências de funcionamento e a diferentes amplitudes. Para além disso, o seu funcionamento foi também validado utilizando uma carga trifásica equilibrada de 3 lâmpadas de forma a ser visualizada a variação de frequência e variação de amplitude.

An high-speed parametric ADC and a co-designed mixer for CMOS RF receivers

Dissertação apresentada na faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para a obtenção do grau de Mestre em Engenharia Electrotécnica e de Computadores

Optimization of multi-stage amplifiers in deep-submicron CMOS using a distributed/parallel genetic algorithm

IEEE International Symposium on Circuits and Systems, pp. 724 – 727, Seattle, EUA