Dual energy versus single energy MDCT: measurement of radiation dose using adult abdominal imaging protocols

RATIONALE AND OBJECTIVES: The aim of this study was to measure the radiation dose of dual-energy and single-energy multidetector computed tomographic (CT) imaging using adult liver, renal, and aortic imaging protocols. MATERIALS AND METHODS: Dual-energy CT (DECT) imaging was performed on a conventional 64-detector CT scanner using a software upgrade (Volume Dual Energy) at tube voltages of 140 and 80 kVp (with tube currents of 385 and 675 mA, respectively), with a 0.8-second gantry revolution time in axial mode. Parameters for single-energy CT (SECT) imaging were a tube voltage of 140 kVp, a tube current of 385 mA, a 0.5-second gantry revolution time, helical mode, and pitch of 1.375:1. The volume CT dose index (CTDI(vol)) value displayed on the console for each scan was recorded. Organ doses were measured using metal oxide semiconductor field-effect transistor technology. Effective dose was calculated as the sum of 20 organ doses multiplied by a weighting factor found in International Commission on Radiological Protection Publication 60. Radiation dose saving with virtual noncontrast imaging reconstruction was also determined. RESULTS: The CTDI(vol) values were 49.4 mGy for DECT imaging and 16.2 mGy for SECT imaging. Effective dose ranged from 22.5 to 36.4 mSv for DECT imaging and from 9.4 to 13.8 mSv for SECT imaging. Virtual noncontrast imaging reconstruction reduced the total effective dose of multiphase DECT imaging by 19% to 28%. CONCLUSION: Using the current Volume Dual Energy software, radiation doses with DECT imaging were higher than those with SECT imaging. Substantial radiation dose savings are possible with DECT imaging if virtual noncontrast imaging reconstruction replaces precontrast imaging.

Investigation of electrically active defects at the interface of high-k dielectrics and compound semiconductors

As silicon based devices in integrated circuits reach the fundamental limits of dimensional scaling there is growing research interest in the use of high electron mobility channel materials, such as indium gallium arsenide (InGaAs), in conjunction with high dielectric constant (high-k) gate oxides, for Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) based devices. The motivation for employing high mobility channel materials is to reduce power dissipation in integrated circuits while also providing improved performance. One of the primary challenges to date in the field of III-V semiconductors has been the observation of high levels of defect densities at the high-k/III-V interface, which prevents surface inversion of the semiconductor. The work presented in this PhD thesis details the characterization of MOS devices incorporating high-k dielectrics on III-V semiconductors. The analysis examines the effect of modifying the semiconductor bandgap in MOS structures incorporating InxGa1-xAs (x: 0, 0.15. 0.3, 0.53) layers, the optimization of device passivation procedures designed to reduce interface defect densities, and analysis of such electrically active interface defect states for the high-k/InGaAs system. Devices are characterized primarily through capacitance-voltage (CV) and conductance-voltage (GV) measurements of MOS structures both as a function of frequency and temperature. In particular, the density of electrically active interface states was reduced to the level which allowed the observation of true surface inversion behavior in the In0.53Ga0.47As MOS system. This was achieved by developing an optimized (NH4)2S passivation, minimized air exposure, and atomic layer deposition of an Al2O3 gate oxide. An extraction of activation energies allows discrimination of the mechanisms responsible for the inversion response. Finally a new approach is described to determine the minority carrier generation lifetime and the oxide capacitance in MOS structures. The method is demonstrated for an In0.53Ga0.47As system, but is generally applicable to any MOS structure exhibiting a minority carrier response in inversion.

The development of planar high-K/III-V p-channel MOSFETs for post-silicon CMOS

Conventional Si complementary-metal-oxide-semiconductor (CMOS) scaling is fast approaching its limits. The extension of the logic device roadmap for future enhancements in transistor performance requires non-Si materials and new device architectures. III-V materials, due to their superior electron transport properties, are well poised to replace Si as the channel material beyond the 10nm technology node to mitigate the performance loss of Si transistors from further reductions in supply voltage to minimise power dissipation in logic circuits. However several key challenges, including a high quality dielectric/III-V gate stack, a low-resistance source/drain (S/D) technology, heterointegration onto a Si platform and a viable III-V p-metal-oxide-semiconductor field-effect-transistor (MOSFET), need to be addressed before III-Vs can be employed in CMOS. This Thesis specifically addressed the development and demonstration of planar III-V p-MOSFETs, to complement the n-MOSFET, thereby enabling an all III-V CMOS technology to be realised. This work explored the application of InGaAs and InGaSb material systems as the channel, in conjunction with Al2O3/metal gate stacks, for p-MOSFET development based on the buried-channel flatband device architecture. The body of work undertaken comprised material development, process module development and integration into a robust fabrication flow for the demonstration of p-channel devices. The parameter space in the design of the device layer structure, based around the III-V channel/barrier material options of In_x≥0.53Ga_1-xAs/In_0.52Al_0.48As and In_x≥0.1Ga_1-xSb/AlSb, was systematically examined to improve hole channel transport. A mobility of 433 cm²/Vs, the highest room temperature hole mobility of any InGaAs quantum-well channel reported to date, was obtained for the In_0.85Ga_0.15As (2.1% strain) structure. S/D ohmic contacts were developed based on thermally annealed Au/Zn/Au metallisation and validated using transmission line model test structures. The effects of metallisation thickness, diffusion barriers and de-oxidation conditions were examined. Contacts to InGaSb-channel structures were found to be sensitive to de-oxidation conditions. A fabrication process, based on a lithographically-aligned double ohmic patterning approach, was realised for deep submicron gate-to-source/drain gap (L_side) scaling to minimise the access resistance, thereby mitigating the effects of parasitic S/D series resistance on transistor performance. The developed process yielded gaps as small as 20nm. For high-k integration on GaSb, ex-situ ammonium sulphide ((NH₄)₂S) treatments, in the range 1%-22%, for 10min at 295K were systematically explored for improving the electrical properties of the Al₂O₃/GaSb interface. Electrical and physical characterisation indicated the 1% treatment to be most effective with interface trap densities in the range of 4 - 10×10¹²cm^-2eV^-1 in the lower half of the bandgap. An extended study, comprising additional immersion times at each sulphide concentration, was further undertaken to determine the surface roughness and the etching nature of the treatments on GaSb. A number of p-MOSFETs based on III-V-channels with the most promising hole transport and integration of the developed process modules were successfully demonstrated in this work. Although the non-inverted InGaAs-channel devices showed good current modulation and switch-off characteristics, several aspects of performance were non-ideal; depletion-mode operation, modest drive current (I_d,sat=1.14mA/mm), double peaked transconductance (g_m=1.06mS/mm), high subthreshold swing (SS=301mV/dec) and high on-resistance (R_on=845kΩ.μm). Despite demonstrating substantial improvement in the on-state metrics of I_d,sat (11×), g_m (5.5×) and R_on (5.6×), inverted devices did not switch-off. Scaling gate-to-source/drain gap (L_side) from 1μm down to 70nm improved I_d,sat (72.4mA/mm) by a factor of 3.6 and gm (25.8mS/mm) by a factor of 4.1 in inverted InGaAs-channel devices. Well-controlled current modulation and good saturation behaviour was observed for InGaSb-channel devices. In the on-state In_0.3Ga_0.7Sb-channel (I_d,sat=49.4mA/mm, g_m=12.3mS/mm, R_on=31.7kΩ.μm) and In_0.4Ga_0.6Sb-channel (I_d,sat=38mA/mm, g_m=11.9mS/mm, R_on=73.5kΩ.μm) devices outperformed the InGaAs-channel devices. However the devices could not be switched off. These findings indicate that III-V p-MOSFETs based on InGaSb as opposed to InGaAs channels are more suited as the p-channel option for post-Si CMOS.

Field-effect transistors fabricated from diluted magnetic semiconductor colloidal nanowires

Field-effect transistors (FETs) fabricated from undoped and Co2+-doped CdSe colloidal nanowires show typical n-channel transistor behaviour with gate effect. Exposed to microscope light, a 10 times current enhancement is observed in the doped nanowire-based devices due to the significant modification of the electronic structure of CdSe nanowires induced by Co2+-doping, which is revealed by theoretical calculations from spin-polarized plane-wave density functional theory.

Phthalocyanato tin(IV) dichloride: An air-stable, high-performance, n-type organic semiconductor with a high field-effect electron mobility

Phthalocyanato tin(IV) dichloride, an axially dichloriniated MPc, is an air-stable high performance n-type organic semiconductor with a field-effect electron mobility of up to 0.30 cm(2) V-1 s(-1). This high mobility together with good device stability and commercial availability makes it a most suitable n-type material for future organic thin-film transistor applications.

Optimization of purification procedures in organic semiconductor synthesis for improving the performances of organic field-effect transistors

The aim of the research activity focused on the investigation of the correlation between the degree of purity in terms of chemical dopants in organic small molecule semiconductors and their electrical and optoelectronic performances once introduced as active material in devices. The first step of the work was addressed to the study of the electrical performances variation of two commercial organic semiconductors after being processed by means of thermal sublimation process. In particular, the p-type 2,2′′′-Dihexyl-2,2′:5′,2′′:5′′,2′′′-quaterthiophene (DH4T) semiconductor and the n-type 2,2′′′- Perfluoro-Dihexyl-2,2′:5′,2′′:5′′,2′′′-quaterthiophene (DFH4T) semiconductor underwent several sublimation cycles, with consequent improvement of the electrical performances in terms of charge mobility and threshold voltage, highlighting the benefits brought by this treatment to the electric properties of the discussed semiconductors in OFET devices by the removal of residual impurities. The second step consisted in the provision of a metal-free synthesis of DH4T, which was successfully prepared without organometallic reagents or catalysts in collaboration with Dr. Manuela Melucci from ISOF-CNR Institute in Bologna. Indeed the experimental work demonstrated that those compounds are responsible for the electrical degradation by intentionally doping the semiconductor obtained by metal-free method by Tetrakis(triphenylphosphine)palladium(0) (Pd(PPh3)4) and Tributyltin chloride (Bu3SnCl), as well as with an organic impurity, like 5-hexyl-2,2':5',2''-terthiophene (HexT3) at, in different concentrations (1, 5 and 10% w/w). After completing the entire evaluation process loop, from fabricating OFET devices by vacuum sublimation with implemented intentionally-doped batches to the final electrical characterization in inherent-atmosphere conditions, commercial DH4T, metal-free DH4T and the intentionally-doped DH4T were systematically compared. Indeed, the fabrication of OFET based on doped DH4T clearly pointed out that the vacuum sublimation is still an inherent and efficient purification method for crude semiconductors, but also a reliable way to fabricate high performing devices.

Field-effect transistors based on self-organized molecular nanostripes

Charge transport properties in organic semiconductors depend strongly on molecular order. Here we demonstrate field-effect transistors where drain current flows through a precisely defined array of nanostripes made of crystalline and highly ordered molecules. The molecular stripes are fabricated across the channel of the transistor by a stamp-assisted deposition of the molecular semiconductors from a solution. As the solvent evaporates, the capillary forces drive the solution to form menisci under the stamp protrusions. The solute precipitates only in the regions where the solution is confined by the menisci once the critical concentration is reached and self-organizes into molecularly ordered stripes 100-200 nm wide and a few monolayers high. The charge mobility measured along the stripes is 2 orders of magnitude larger than the values measured for spin-coated thin films.

Charge carrier velocity distributions in high mobility polymer field-effect transistors

In this letter, the velocity distributions of charge carriers in high-mobility polymer thin-film transistors (TFTs) with a diketopyrrolopyrrole- naphthalene copolymer (PDPP-TNT) semiconductor active layer are reported. The velocity distributions are found to be strongly dependent on measurement temperatures as well as annealing conditions. Considerable inhomogeneity is evident at low measurement temperatures and for low annealing temperatures. Such transient transport measurements can provide additional information about charge carrier transport in TFTs which are unavailable using steady-state transport measurements.

Solution-processed dual-gate polymer field-effect transistors for display applications

We describe the advantages of dual-gate thin-film transistors (TFTs) for display applications. We show that in TFTs with active semiconductor layers composed of diketopyrrolopyrrole-naphthalene copolymer, the on-current is increased, the off-current is reduced, and the sub-threshold swing is improved compared to single-gate devices. Charge transport measurements in steady-state and under non-quasi-static conditions reveal the reasons for this improved performance. We show that in dual-gate devices, a much smaller fraction of charge carriers move in slow trap states. We also compare the activation energies for charge transport in the top-gate and bottom-gate configurations.

Isoindigo dye incorporated copolymers with naphthalene and anthracene: promising materials for stable organic field effect transistors

In this paper, we report the design and synthesis of isoindigo based low band gap polymer semiconductors, poly{N,N′-(2-octyldodecyl)-isoindigo-alt- naphthalene} (PISD-NAP) and poly{N,N′-(2-octyldodecyl)-isoindigo-alt- anthracene} (PISD-ANT). A series of donor-acceptor (D-A) copolymers can be prepared where donor and acceptor conjugated blocks can be attached alternately using organometallic coupling. In these polymers, an isoindigo dye acceptor moiety has been attached alternately with naphthalene and anthracene donor comonomer blocks by Suzuki coupling. PISD-NAP and PISD-ANT exhibit excellent solution processibility and good film-forming properties. Gel permeation chromatography exhibits a higher molecular mass with lower polydispersity. UV-vis-NIR absorption of these polymers exhibits a wide absorption band ranging from 300 nm to 800 nm, indicating the low band gap nature of the polymers. Optical band gaps calculated from the solid state absorption cutoff value for PISD-NAP and PISD-ANT are around 1.80 eV and 1.75 eV, respectively. Highest occupied molecular orbital (HOMO) values calculated respectively for PISD-NAP and PISD-ANT thin films on glass substrate by photoelectron spectroscopy in air (PESA) are 5.66 eV and 5.53 eV, indicative of the good stability of these materials in organic electronic device applications. These polymers exhibit p-channel charge transport characteristics when used as the active semiconductor in organic thin-film transistor (OTFT) devices in ambient conditions. The highest hole mobility of 0.013 cm2 V-1 s-1 is achieved in top contact and bottom-gate OTFT devices for PISD-ANT, whereas polymer PISD-NAP exhibited a hole mobility of 0.004 cm2 V -1 s-1. When these polymer semiconductors were used as a donor and PC71BM as an acceptor in OPV devices, the highest power conversion efficiency (PCE) of 1.13% is obtained for the PISD-ANT polymer.

Field-Effect and Frequency Dependent Transport in Semiconductor-Enriched Single-Wall Carbon Nanotube Network Device

The electrical and optical response of a field-effect device comprising a network of semiconductor-enriched single-wall carbon nanotubes, gated with sodium chloride solution is investigated. Field-effect is demonstrated in a device that uses facile fabrication techniques along with a small-ion as the gate electrolyte-and this is accomplished as a result of the semiconductor enhancement of the tubes. The optical transparency and electrical resistance of the device are modulated with gate voltage. A time-response study of the modulation of optical transparency and electrical resistance upon application of gate voltage suggests the percolative charge transport in the network. Also the ac response in the network is investigated as a function of frequency and temperature down to 5 K. An empirical relation between onset frequency and temperature is determined.

Impact of energy quantisation in single electron transistor island on hybrid complementary metal oxide semiconductor-single electron transistor integrated circuits

For the first time, the impact of energy quantisation in single electron transistor (SET) island on the performance of hybrid complementary metal oxide semiconductor (CMOS)-SET transistor circuits has been studied. It has been shown through simple analytical models that energy quantisation primarily increases the Coulomb Blockade area and Coulomb Blockade oscillation periodicity of the SET device and thus influences the performance of hybrid CMOS-SET circuits. A novel computer aided design (CAD) framework has been developed for hybrid CMOS-SET co-simulation, which uses Monte Carlo (MC) simulator for SET devices along with conventional SPICE for metal oxide semiconductor devices. Using this co-simulation framework, the effects of energy quantisation have been studied for some hybrid circuits, namely, SETMOS, multiband voltage filter and multiple valued logic circuits. Although energy quantisation immensely deteriorates the performance of the hybrid circuits, it has been shown that the performance degradation because of energy quantisation can be compensated by properly tuning the bias current of the current-biased SET devices within the hybrid CMOS-SET circuits. Although this study is primarily done by exhaustive MC simulation, effort has also been put to develop first-order compact model for SET that includes energy quantisation effects. Finally, it has been demonstrated that one can predict the SET behaviour under energy quantisation with reasonable accuracy by slightly modifying the existing SET compact models that are valid for metallic devices having continuous energy states.

Performance limits of transition metal dichalcogenide (MX2) nanotube surround gate ballistic field effect transistors

We theoretically analyze the performance of transition metal dichalcogenide (MX2) single wall nanotube (SWNT) surround gate MOSFET, in the 10 nm technology node. We consider semiconducting armchair (n, n) SWNT of MoS2, MoSe2, WS2, and WSe2 for our study. The material properties of the nanotubes are evaluated from the density functional theory, and the ballistic device characteristics are obtained by self-consistently solving the Poisson-Schrodinger equation under the non-equilibrium Green's function formalism. Simulated ON currents are in the range of 61-76 mu A for 4.5 nm diameter MX2 tubes, with peak transconductance similar to 175-218 mu S and ON/OFF ratio similar to 0.6 x 10(5)-0.8 x 10(5). The subthreshold slope is similar to 62.22 mV/decade and a nominal drain induced barrier lowering of similar to 12-15 mV/V is observed for the devices. The tungsten dichalcogenide nanotubes offer superior device output characteristics compared to the molybdenum dichalcogenide nanotubes, with WSe2 showing the best performance. Studying SWNT diameters of 2.5-5 nm, it is found that increase in diameter provides smaller carrier effective mass and 4%-6% higher ON currents. Using mean free path calculation to project the quasi-ballistic currents, 62%-75% reduction from ballistic values in drain current in long channel lengths of 100, 200 nm is observed.