Transmission loss allocation in a deregulated electrical energy market

This paper presents a new method for transmission loss allocation in a deregulated electrical power market. The proposed method is based on physical flow through transmission lines. The contributions of individual loads to the line flows are used as basis for allocating transmission losses to different loads. With minimum assumptions, that sound to be reasonable and cannot be rejected, a novel loss allocation formula is derived. The assumptions made are: a number of currents sharing a transmission line distribute themselves over the cross section in the same manner; that distribution causes the minimum possible power loss. Application of the proposed method is straightforward. It requires only a solved power flow and any simple algorithm for power flow tracing. Both active and reactive powers are considered in the loss allocation procedure. Results of application show the accuracy of the proposed method compared with the commonly used procedures.

Creation of damage-free ferroelectric nanocapacitors via focused ion beam milling

We present a novel method for creating damage-free ferroelectric nanostructures with a focused ion beam milling machine. Using a standard e-beam photoresist followed by a dilute acid wash, nanostructures ranging in size from 1 mu m down to 250 nm were created in a 90 nm thick lead zirconate titanate ( PZT) wafer. Transmission electron microscopy and piezoresponse force microscopy ( PFM) confirmed that the surfaces of the nanostructures remained damage free during fabrication, and showed no gallium implantation, and that there was no degradation of ferroelectric properties. In fact DC strain loops, obtained using PFM, demonstrated that the nanostructures have a higher piezoresponse than unmilled films. As the samples did not have any top hard mask, the method presented is unique as it allows for imaging of the top surface to understand edge effects in well-defined nanostructures. In addition, as no post-mill annealing was necessary, it facilitates investigation of nanoscale domain mechanisms without process-induced artefacts.

Ancients inspire modern memory

A stencilling technique for depositing arrays of nanoscale ferroelectric capacitors on a surface could be useful in data storage devices.

Liquid source misted chemical deposition process of three-dimensional nano-ferroelectrics with substrate heating

A modification of liquid source misted chemical deposition process (LSMCD) with heating mist and substrate has developed, and this enabled to control mist penetrability and fluidity on sidewalls of three-dimensional structures and ensure step coverage. A modified LSMCD process allowed a combinatorial approach of Pb(Zr,Ti)O-3 (PZT) thin films and carbon nanotubes (CNTs) toward ultrahigh integration density of ferroelectric random access memories (FeRAMs). The CNTs templates were survived during the crystallization process of deposited PZT film onto CNTs annealed at 650 degrees C in oxygen ambient due to a matter of minute process, so that the thermal budget is quite small. The modified LSMCD process opens up the possibility to realize the nanoscale capacitor structure of ferroelectric PZT film with CNTs electrodes toward ultrahigh integration density FeRAMs.

Characterization of T-type calcium current and its contribution to electrical activity in rabbit urethra.

Rabbit urethral smooth muscle cells were studied at 37 degrees C by using the amphotericin B perforated-patch configuration of the patch-clamp technique, using Cs(+)-rich pipette solutions. Two components of current, with electrophysiological and pharmacological properties typical of T- and L-type Ca(2+) currents, were recorded. Fitting steady-state inactivation curves for the L current with a Boltzmann equation yielded a V(1/2) of -41 +/- 3 mV. In contrast, the T current inactivated with a V(1/2) of -76 +/- 2 mV. The L currents were reduced by nifedipine (IC(50) = 225 +/- 84 nM), Ni(2+) (IC(50) = 324 +/- 74 microM), and mibefradil (IC(50) = 2.6 +/- 1.1 microM) but were enhanced when external Ca(2+) was substituted with Ba(2+). The T current was little affected by nifedipine at concentrations

Electrical activity induced by nitric oxide in canine colonic circular muscle.

Nitric oxide generates slow electrical oscillations (SEOs) in cells near the myenteric edge of the circular muscle layer, which resemble slow waves generated by interstitial cells of Cajal (ICCs) at the submucosal edge of this muscle. The properties of SEOs were studied to determine whether these events are similar to slow waves. Rapid frequency membrane potential oscillations (MPOs; 16 +/- 1 cycles/min and 9.6 +/- 0.2 mV) were recorded from control muscles near the myenteric edge. Sodium nitroprusside (0.3 microM) reduced MPOs and initiated SEOs (1.3 +/- 0.3 cycles/min and 13.4 +/- 1.4 mV amplitude). SEOs were abolished by the guanylate cyclase inhibitor 1H-[1,2,4]-oxadiazolo-[4,3-a]-quinoxaline-1-one (10 microM). MPOs were abolished by nifedipine (1 microM), whereas SEO frequency increased and the amount of depolarization decreased. BAY K 8644 (1 microM) prolonged SEOs and reduced their frequency. SEOs were abolished by Ni(2+) (0.5 mM), low Ca(2+) solution (0.1 mM Ca(2+)), cyclopiazonic acid (10 microM), and the mitochondrial uncouplers antimycin (10 microM) and carbonyl cyanide p-trifluoromethoxyphenylhydrazone (1 microM). Oligomycin (10 microM) was without effect. These effects are similar to those described for colonic slow waves. Our results suggest that nitric oxide-induced SEOs are similar in mechanism to slow waves, an activity not previously thought to be generated by myenteric pacemakers.

High tolerance to gate misalignment in low voltage gate-underlap double gate MOSFETs

.In this letter, we demonstrate for the first time that gate misalignment is not a critical limiting factor for low voltage operation in gate-underlap double gate (DG) devices. Our results show that underlap architecture significantly extends the tolerable limit of gate misalignment in 25 nm devices. DG MOSFETs with high degree of gate misalignment and optimal gate-underlap design can perform comparably or even better than self-aligned nonunderlap devices. Results show that spacer-to-straggle (s/sigma) ratio, a key design parameter for underlap devices, should be within the range of 2.3-3.0 to accommodate back gate misalignment. These results are very significant as the stringent process control requirements for achieving self-alignment in nanoscale planar DG MOSFETs are considerably relaxed

Performance projections and design optimization of planar double gate SOI MOSFETs for logic technology applications

In this paper, by investigating the influence of source/drain extension region engineering (also known as gate-source/drain underlap) in nanoscale planar double gate (DG) SOI MOSFETs, we offer new insights into the design of future nanoscale gate-underlap DG devices to achieve ITRS projections for high performance (HP), low standby power (LSTP) and low operating power (LOP) logic technologies. The impact of high-kappa gate dielectric, silicon film thickness, together with parameters associated with the lateral source/drain doping profile, is investigated in detail. The results show that spacer width along with lateral straggle can not only effectively control short-channel effects, thus presenting low off-current in a gate underlap device, but can also be optimized to achieve lower intrinsic delay and higher on-off current ratio (I-on/I-off). Based on the investigation of on-current (I-on), off-current (I-off), I-on/I-off, intrinsic delay (tau), energy delay product and static power dissipation, we present design guidelines to select key device parameters to achieve ITRS projections. Using nominal gate lengths for different technologies, as recommended from ITRS specification, optimally designed gate-underlap DG MOSFETs with a spacer-to-straggle (s/sigma) ratio of 2.3 for HP/LOP and 3.2 for LSTP logic technologies will meet ITRS projection. However, a relatively narrow range of lateral straggle lying between 7 to 8 nm is recommended. A sensitivity analysis of intrinsic delay, on-current and off-current to important parameters allows a comparative analysis of the various design options and shows that gate workfunction appears to be the most crucial parameter in the design of DG devices for all three technologies. The impact of back gate misalignment on I-on, I-off and tau is also investigated for optimized underlap devices.

Design and optimization of FinFETs for ultra-low-voltage analog applications

In this paper, we analyze the enormous potential of engineering source/drain extension (SDE) regions in FinFETs for ultra-low-voltage (ULV) analog applications. SDE region design can simultaneously improve two key analog figures of merit (FOM)-intrinsic de gain (A(vo)) and cutoff frequency (f(T)) for 60 and 30 nm FinFETs operated at low drive current (J(ds) = 5 mu A/mu m). The improved Avo and fT are nearly twice compared to those of devices with abrupt SDE regions. The influence of the SDE region profile and its impact on analog FOM is extensively analyzed. Results show that SDE region optimization provides an additional degree of freedom apart from device parameters (fin width and aspect ratio) to design future nanoscale analog devices. The results are analyzed in terms of spacer-to-straggle ratio a new design parameter for SDE engineered devices. This paper provides new opportunities for realizing future ULV/low-power analog design with FinFETs.

Source/drain extension region engineering in FinFETs for low-voltage analog applications

In this letter, we propose a novel design methodology for engineering source/drain extension (SDE) regions to simultaneously improve intrinsic dc gain (A(vo)) and cutoff frequency (f(T)) of 25-nm gate-length FinFETs operated at low drain-current (I-ds = 10 mu A/mu m). SDE region optimization in 25-nm FinFETs results in exceptionally high values of Avo (similar to 45 dB) and f(T) (similar to 70 GHz), which is nearly 2.5 times greater when compared to devices designed with abrupt SDE regions. The influence of spacer width, lateral source/drain doping gradient, and the spacer-to-gradient ratio on key analog figures of merit is examined in detail. This letter provides new opportunities for realizing future low-voltage/low-power analog design with nanoscale SDE-engineered FinFETs.

Analog performance of double gate SOI transistors

Double gate fully depleted silicon-on-insulator (DGSOI) is recognized as a possible solution when the physical gate length L-G reduces to 25nm for the 65nm node on the ITRS CMOS roadmap. In this paper, scaling guidelines are introduced to optimally design a nanoscale DGSOI. For this reason, the sensitivity of gain, f(T) and f(max) to each of the key geometric and technological parameters of the DGSOI are assessed and quantified using MixedMode simulation. The impact of the parasitic resistance and capacitance on analog device performance is systematically analysed. By comparing analog performance with a single gate (SG), it has been found that intrinsic gain in DGSOI is 4 times higher but its fT was found to be comparable to that of SGSOI at different regions of transistor operation. However, the extracted fmax in SG SOI was higher (similar to 40%) compared to DGSOI due to its lower capacitance.